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The PL022 PrimeCell Synchronous Serial Port (SSP) is an AMBA compliant SoC peripheral that is developed, tested, and licensed by ARM Limited.
Table 4.69. SSP implementation
| Property | Value |
|---|---|
| Location | FPGA |
| Memory base address | 0x1000D000 |
| Interrupt | 11 |
| DMA | 9 for transmit 8 for receive |
| Release version | ARM SSP PL022 r1p2 |
| Reference documentation | ARM PrimeCell Synchronous Serial Port Controller (PL022) Technical Reference Manual (see also Synchronous Serial Port, SSP) |
The SSP functions as a master or slave interface that enables synchronous serial communication with slave or master peripherals having one of the following:
a Motorola SPI-compatible interface
a Texas Instruments synchronous serial interface
a National Semiconductor Microwire interface.
In both master and slave configurations, the PrimeCell SSP performs:
parallel-to-serial conversion on data written to a transmit FIFO
serial-to-parallel conversion and FIFO buffering of received data.
Interrupts are generated to:
request servicing of the transmit and receive FIFO
inform the system that a receive FIFO over-run has occurred
inform the system that data is present in the receive FIFO.
The SSP controller can be shared with the following resources:
If the LCD adaptor board is fitted with a touch screen, the controller interfaces to the SSP port to provide touch screen, keypad, LCD bias and analogue inputs. See the LCD adaptor board TSCI appendix for further details.
Use the SYS_CLCD register to control the SSP chip selects. See CLCD Control Register, SYS_CLCD.
An off board SSP device, such as an EEPROM, can be connected to expansion header. If you connect both the LCD adaptor board and the off board SSP device at the same time, ensure the correct SSP interface protocol is used when communicating with each device.
Synthesized SSP peripherals in a Logic Tile FPGA can be connected using the tile expansion connectors.