| Copyright © 2005-2011 ARM Limited. All rights reserved. | ARM DUI 0303E |
| Non-Confidential | |
 PDF version | |
| Home > Programmer’s Reference > Watchdog |
| |||
| Home > Programmer’s Reference > Watchdog | |||
The SP805 Watchdog module is an AMBA compliant SoC peripheral developed, tested and licensed by ARM Limited. The Watchdog module consists of a 32-bit down counter with a programmable timeout interval that has the capability to generate an interrupt and a reset signal on timing out. It is intended to be used to apply a reset to a system in the event of a software failure.
The Watchdog counter is disabled if the core is in debug state.
Table 4.78. Watchdog implementation
| Property | Value |
|---|---|
| Location | FPGA |
| Memory base address | 0x10010000 |
| Interrupt | 0 |
| DMA | NA |
| Release version | ARM WDOG SP805 r1p0-02ltd0 |
| Reference documentation | ARM PrimeCell Watchdog Controller (SP805) Technical Reference Manual |
The following Watchdog module parameters are programmable:
interrupt generation enable/disable
interrupt masking
reset signal generation enable/disable
interrupt interval.
| Copyright © 2005-2011 ARM Limited. All rights reserved. | ARM DUI 0303E |
| Non-Confidential | |
| PDF version | |
| Home > Programmer’s Reference > Watchdog |