4.6.1. Display resolutions and display memory organization

Different display resolutions require different data and synchronization timing. Use registers CLCD_TIM0, CLCD_TIM1, CLCD_TIM2, and SYS_OSCCLK4 to define the display timings. Table 4.35 lists the register and clock values for different display resolutions.

Table 4.35. Values for different display resolutions

Display resolutionCLCDCLK frequency and SYS_OSCCLK4 register value CLCD_TIM0 register at 0x10020000CLCD_TIM1 register 0x10020004CLCD_TIM2 register at 0x10020008
QVGA(240x320) (portrait) on VGA25MHz, 0x2C770xC7A7BF380x595B613F0x04eF1800
QVGA (320x240) (landscape) on VGA25MHz, 0x2C770x9F7FBF4C0x818360eF0x053F1800
QCIF (176x220) (portrait) on VGA25MHz, 0x2C770xe7C7BF280x8B8D60DB0x04AF1800
VGA (640x480) on VGA25MHz, 0x2C770x3F1F3F9C0x090B61DF0x067F1800
SVGA (800x600) on SVGA36MHz, 0x2CAC0x1313A4C40x0505F6570x071F1800
Epson 2.2in panel QCIF (176x220)16MHz, 0x2C480x020102280x010004DB0x04AF3800
Sanyo 3.8in panel QVGA (320x240)10MHz, 0x2C2A0x0505054C0x050514eF0x053F1800

The mapping of the 32 bits of pixel data in memory to the RGB display signals depends on the resolution and display mode.

Note

Rx, Gx, and Bx in Table 4.36 lists the memory bits used to set the red, green, and blue brightness for direct (non-palettized) 24 and 16-bit color modes.

For resolutions based on one to sixteen bits per pixel, multiple pixels are encoded into each 32-bit word.

All monochrome modes, and color modes using 8 or fewer bits per pixel, use the palette to encode the color value from the data bits. For details on using the palette RAM, see the CLCD Technical Reference Manual.

Memory encoding for one to eight bits per pixel are listed in Table 4.38. The bit correspondence in the table is based on little-endian byte and little-endian pixel encoding.

Table 4.36. Assignment of display memory to R[7:0], G[7:0], and B[7:0]

Memory bit 8/8/8 1/5/5/5 5/6/54/4/4
31unused pixel1 I (intensity) pixel1 R4 (msb) unused
30unusedpixel1 B4 (msb) pixel1 R3unused
29unusedpixel1 B3pixel1 R2unused
28unusedpixel1 B2pixel1 R1unused
27unusedpixel1 B1 pixel1 R0 (lsb) pixel1 B3
26unusedpixel1 B0 (lsb) pixel1 G5 (msb)pixel1 B2
25unusedpixel1 G4 (msb) pixel1 G4pixel1 B1
24unusedpixel1 G3pixel1 G3pixel1 B0 (lsb)
23B7 (msb) pixel1 G2pixel1 G2pixel1 G3
22B6 pixel1 G1pixel1 G1pixel1 G2
21B5 pixel1 G0 (lsb) pixel1 G0 (lsb)pixel1 G1
20B4 pixel1 R4 (msb) pixel1 B4 (msb) pixel1 G0 (lsb)
19B3 pixel1 R3pixel1 B3pixel1 R3
18B2 pixel1 R2pixel1 B2pixel1 R2
17B1 pixel1 R1pixel1 B1 pixel1 R1
16B0 (lsb) pixel1 R0 (lsb) pixel1 B0pixel1 R0 (lsb)
15G7 (msb) pixel0 I (intensity) pixel0 B4 (msb)unused
14G6 pixel0 B4pixel0 B2unused
13G5 pixel0 B3pixel0 B2unused
12G4 pixel0 B2pixel0 B1unused
11G3 pixel0 B1 pixel0 B0 (lsb)pixel0 B3
10G2 pixel0 B0 (lsb) pixel0 G5 (msb)pixel0 B2
9 G1 pixel0 G4 (msb) pixel0 G4pixel0 B1
8 G0 (lsb) pixel0 G3pixel0 G3pixel0 B0 (lsb)
7 R7 (msb) pixel0 G2pixel0 G2pixel0 G3
6 R6 pixel0 G1pixel0 G1pixel0 G2
5 R5 pixel0 G0 (lsb) pixel0 G0 (lsb)pixel0 G1
4 R4 pixel0 R4 (msb) pixel0 R4 (msb)pixel0 G0 (lsb)
3 R3 pixel0 R3 pixel0 R3pixel0 R3
2 R2 pixel0 R2pixel0 R2pixel0 R2
1 R1 pixel0 R1pixel0 R2pixel0 R1
0 R0 (lsb) pixel0 I (intensity) pixel0 R0 (lsb)pixel0 R0 (lsb)

Table 4.37. Assignment of display memory for 8, 4, 2, and 1 bits per pixel

Memory bit 8 bits per pixel4 bits per pixel2 bits per pixel1 bit per pixel
31pixel 3 X7pixel 7 X3pixel 15 X1pixel 31
30pixel 3 X6pixel 7 X2pixel 15 X0pixel 30
29pixel 3 X5pixel 7 X1pixel 14 X1pixel 29
28pixel 3 X4pixel 7 X0pixel 14 X0pixel 28
27pixel 3 X3pixel 6 X3pixel 13 X1pixel 27
26pixel 3 X2pixel 6 X2pixel 13 X0pixel 26
25pixel 3 X1pixel 6 X1pixel 12 X1pixel 25
24pixel 3 X0pixel 6 X0pixel 12 X0pixel 24
23pixel 2 X7pixel 5 X3pixel 11 X1pixel 23
22pixel 2 X6pixel 5 X2pixel 11 X0pixel 22
21pixel 2 X5pixel 5 X1pixel 10 X1pixel 21
20pixel 2 X4pixel 5 X0pixel 10 X0pixel 20
19pixel 2 X3pixel 4 X3pixel 9 X1pixel 19
18pixel 2 X2pixel 4 X2pixel 9 X0pixel 18
17pixel 2 X1pixel 4 X1pixel 8 X1pixel 17
16pixel 2 X0pixel 4 X0pixel 8 X0pixel 16
15pixel 1 X7pixel 3 X3pixel 7 X1pixel 15
14pixel 1 X6pixel 3 X2pixel 7 X0pixel 14
13pixel 1 X5pixel 3 X1pixel 6 X1pixel 13
12pixel 1 X4pixel 3 X0pixel 6 X0pixel 12
11pixel 1 X3pixel 2 X3pixel 5 X1pixel 11
10pixel 1 X2pixel 2 X2pixel 5 X0pixel 10
9 pixel 1 X1pixel 2 X1pixel 4 X1pixel 9
8 pixel 1 X0pixel 2 X0pixel 4 X0pixel 8
7 pixel 0 X7pixel 1 X3pixel 3 X1pixel 7
6 pixel 0 X6pixel 1 X2pixel 3 X0pixel 6
5 pixel 0 X5pixel 1 X1pixel 2 X1pixel 5
4 pixel 0 X4pixel 1 X0pixel 2 X0pixel 4
3 pixel 0 X3pixel 0 X3pixel 1 X1pixel 3
2 pixel 0 X2pixel 0 X2pixel 1 X0pixel 2
1 pixel 0 X1pixel 0 X1pixel 0 X1pixel 1
0 pixel 0 X0pixel 0 X0pixel 0 X0pixel 0

Table 4.38. Assignment of display memory to pixels

Memory bit 8 bits per pixel4 bits per pixel2 bits per pixel1 bit per pixel
31pixel 3 X7pixel 7 X3pixel 15 X1pixel 31
30pixel 3 X6pixel 7 X2pixel 15 X0pixel 30
29pixel 3 X5pixel 7 X1pixel 14 X1pixel 29
28pixel 3 X4pixel 7 X0pixel 14 X0pixel 28
27pixel 3 X3pixel 6 X3pixel 13 X1pixel 27
26pixel 3 X2pixel 6 X2pixel 13 X0pixel 26
25pixel 3 X1pixel 6 X1pixel 12 X1pixel 25
24pixel 3 X0pixel 6 X0pixel 12 X0pixel 24
23pixel 2 X7pixel 5 X3pixel 11 X1pixel 23
22pixel 2 X6pixel 5 X2pixel 11 X0pixel 22
21pixel 2 X5pixel 5 X1pixel 10 X1pixel 21
20pixel 2 X4pixel 5 X0pixel 10 X0pixel 20
19pixel 2 X3pixel 4 X3pixel 9 X1pixel 19
18pixel 2 X2pixel 4 X2pixel 9 X0pixel 18
17pixel 2 X1pixel 4 X1pixel 8 X1pixel 17
16pixel 2 X0pixel 4 X0pixel 8 X0pixel 16
15pixel 1 X7pixel 3 X3pixel 7 X1pixel 15
14pixel 1 X6pixel 3 X2pixel 7 X0pixel 14
13pixel 1 X5pixel 3 X1pixel 6 X1pixel 13
12pixel 1 X4pixel 3 X0pixel 6 X0pixel 12
11pixel 1 X3pixel 2 X3pixel 5 X1pixel 11
10pixel 1 X2pixel 2 X2pixel 5 X0pixel 10
9 pixel 1 X1pixel 2 X1pixel 4 X1pixel 9
8 pixel 1 X0pixel 2 X0pixel 4 X0pixel 8
7 pixel 0 X7pixel 1 X3pixel 3 X1pixel 7
6 pixel 0 X6pixel 1 X2pixel 3 X0pixel 6
5 pixel 0 X5pixel 1 X1pixel 2 X1pixel 5
4 pixel 0 X4pixel 1 X0pixel 2 X0pixel 4
3 pixel 0 X3pixel 0 X3pixel 1 X1pixel 3
2 pixel 0 X2pixel 0 X2pixel 1 X0pixel 2
1 pixel 0 X1pixel 0 X1pixel 0 X1pixel 1
0 pixel 0 X0pixel 0 X0pixel 0 X0pixel 0

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