RealView Emulation Baseboard User Guide: 4.6.1. Display resolutions and display memory organization

4.6.1. Display resolutions and display memory organization

Different display resolutions require different data and synchronization timing. Use registers CLCD_TIM0, CLCD_TIM1, CLCD_TIM2, and SYS_OSCCLK4 to define the display timings. Table 4.35 lists the register and clock values for different display resolutions.

Table 4.35. Values for different display resolutions

Display resolution	CLCDCLK frequency and SYS_OSCCLK4 register value	CLCD_TIM0 register at 0x10020000	CLCD_TIM1 register 0x10020004	CLCD_TIM2 register at 0x10020008
QVGA(240x320) (portrait) on VGA	25MHz, `0x2C77`	`0xC7A7BF38`	`0x595B613F`	`0x04eF1800`
QVGA (320x240) (landscape) on VGA	25MHz, `0x2C77`	`0x9F7FBF4C`	`0x818360eF`	`0x053F1800`
QCIF (176x220) (portrait) on VGA	25MHz, `0x2C77`	`0xe7C7BF28`	`0x8B8D60DB`	`0x04AF1800`
VGA (640x480) on VGA	25MHz, `0x2C77`	`0x3F1F3F9C`	`0x090B61DF`	`0x067F1800`
SVGA (800x600) on SVGA	36MHz, `0x2CAC`	`0x1313A4C4`	`0x0505F657`	`0x071F1800`
Epson 2.2in panel QCIF (176x220)	16MHz, `0x2C48`	`0x02010228`	`0x010004DB`	`0x04AF3800`
Sanyo 3.8in panel QVGA (320x240)	10MHz, `0x2C2A`	`0x0505054C`	`0x050514eF`	`0x053F1800`

The mapping of the 32 bits of pixel data in memory to the RGB display signals depends on the resolution and display mode.

Note

Rx, Gx, and Bx in Table 4.36 lists the memory bits used to set the red, green, and blue brightness for direct (non-palettized) 24 and 16-bit color modes.

For resolutions based on one to sixteen bits per pixel, multiple pixels are encoded into each 32-bit word.

All monochrome modes, and color modes using 8 or fewer bits per pixel, use the palette to encode the color value from the data bits. For details on using the palette RAM, see the CLCD Technical Reference Manual.

Memory encoding for one to eight bits per pixel are listed in Table 4.38. The bit correspondence in the table is based on little-endian byte and little-endian pixel encoding.

Table 4.36. Assignment of display memory to R[7:0], G[7:0], and B[7:0]

Memory bit	8/8/8	1/5/5/5	5/6/5	4/4/4
31	unused	pixel1 I (intensity)	pixel1 R4 (msb)	unused
30	unused	pixel1 B4 (msb)	pixel1 R3	unused
29	unused	pixel1 B3	pixel1 R2	unused
28	unused	pixel1 B2	pixel1 R1	unused
27	unused	pixel1 B1	pixel1 R0 (lsb)	pixel1 B3
26	unused	pixel1 B0 (lsb)	pixel1 G5 (msb)	pixel1 B2
25	unused	pixel1 G4 (msb)	pixel1 G4	pixel1 B1
24	unused	pixel1 G3	pixel1 G3	pixel1 B0 (lsb)
23	B7 (msb)	pixel1 G2	pixel1 G2	pixel1 G3
22	B6	pixel1 G1	pixel1 G1	pixel1 G2
21	B5	pixel1 G0 (lsb)	pixel1 G0 (lsb)	pixel1 G1
20	B4	pixel1 R4 (msb)	pixel1 B4 (msb)	pixel1 G0 (lsb)
19	B3	pixel1 R3	pixel1 B3	pixel1 R3
18	B2	pixel1 R2	pixel1 B2	pixel1 R2
17	B1	pixel1 R1	pixel1 B1	pixel1 R1
16	B0 (lsb)	pixel1 R0 (lsb)	pixel1 B0	pixel1 R0 (lsb)
15	G7 (msb)	pixel0 I (intensity)	pixel0 B4 (msb)	unused
14	G6	pixel0 B4	pixel0 B2	unused
13	G5	pixel0 B3	pixel0 B2	unused
12	G4	pixel0 B2	pixel0 B1	unused
11	G3	pixel0 B1	pixel0 B0 (lsb)	pixel0 B3
10	G2	pixel0 B0 (lsb)	pixel0 G5 (msb)	pixel0 B2
9	G1	pixel0 G4 (msb)	pixel0 G4	pixel0 B1
8	G0 (lsb)	pixel0 G3	pixel0 G3	pixel0 B0 (lsb)
7	R7 (msb)	pixel0 G2	pixel0 G2	pixel0 G3
6	R6	pixel0 G1	pixel0 G1	pixel0 G2
5	R5	pixel0 G0 (lsb)	pixel0 G0 (lsb)	pixel0 G1
4	R4	pixel0 R4 (msb)	pixel0 R4 (msb)	pixel0 G0 (lsb)
3	R3	pixel0 R3	pixel0 R3	pixel0 R3
2	R2	pixel0 R2	pixel0 R2	pixel0 R2
1	R1	pixel0 R1	pixel0 R2	pixel0 R1
0	R0 (lsb)	pixel0 I (intensity)	pixel0 R0 (lsb)	pixel0 R0 (lsb)

Table 4.37. Assignment of display memory for 8, 4, 2, and 1 bits per pixel

Memory bit	8 bits per pixel	4 bits per pixel	2 bits per pixel	1 bit per pixel
31	pixel 3 X7	pixel 7 X3	pixel 15 X1	pixel 31
30	pixel 3 X6	pixel 7 X2	pixel 15 X0	pixel 30
29	pixel 3 X5	pixel 7 X1	pixel 14 X1	pixel 29
28	pixel 3 X4	pixel 7 X0	pixel 14 X0	pixel 28
27	pixel 3 X3	pixel 6 X3	pixel 13 X1	pixel 27
26	pixel 3 X2	pixel 6 X2	pixel 13 X0	pixel 26
25	pixel 3 X1	pixel 6 X1	pixel 12 X1	pixel 25
24	pixel 3 X0	pixel 6 X0	pixel 12 X0	pixel 24
23	pixel 2 X7	pixel 5 X3	pixel 11 X1	pixel 23
22	pixel 2 X6	pixel 5 X2	pixel 11 X0	pixel 22
21	pixel 2 X5	pixel 5 X1	pixel 10 X1	pixel 21
20	pixel 2 X4	pixel 5 X0	pixel 10 X0	pixel 20
19	pixel 2 X3	pixel 4 X3	pixel 9 X1	pixel 19
18	pixel 2 X2	pixel 4 X2	pixel 9 X0	pixel 18
17	pixel 2 X1	pixel 4 X1	pixel 8 X1	pixel 17
16	pixel 2 X0	pixel 4 X0	pixel 8 X0	pixel 16
15	pixel 1 X7	pixel 3 X3	pixel 7 X1	pixel 15
14	pixel 1 X6	pixel 3 X2	pixel 7 X0	pixel 14
13	pixel 1 X5	pixel 3 X1	pixel 6 X1	pixel 13
12	pixel 1 X4	pixel 3 X0	pixel 6 X0	pixel 12
11	pixel 1 X3	pixel 2 X3	pixel 5 X1	pixel 11
10	pixel 1 X2	pixel 2 X2	pixel 5 X0	pixel 10
9	pixel 1 X1	pixel 2 X1	pixel 4 X1	pixel 9
8	pixel 1 X0	pixel 2 X0	pixel 4 X0	pixel 8
7	pixel 0 X7	pixel 1 X3	pixel 3 X1	pixel 7
6	pixel 0 X6	pixel 1 X2	pixel 3 X0	pixel 6
5	pixel 0 X5	pixel 1 X1	pixel 2 X1	pixel 5
4	pixel 0 X4	pixel 1 X0	pixel 2 X0	pixel 4
3	pixel 0 X3	pixel 0 X3	pixel 1 X1	pixel 3
2	pixel 0 X2	pixel 0 X2	pixel 1 X0	pixel 2
1	pixel 0 X1	pixel 0 X1	pixel 0 X1	pixel 1
0	pixel 0 X0	pixel 0 X0	pixel 0 X0	pixel 0

Table 4.38. Assignment of display memory to pixels

Memory bit	8 bits per pixel	4 bits per pixel	2 bits per pixel	1 bit per pixel
31	pixel 3 X7	pixel 7 X3	pixel 15 X1	pixel 31
30	pixel 3 X6	pixel 7 X2	pixel 15 X0	pixel 30
29	pixel 3 X5	pixel 7 X1	pixel 14 X1	pixel 29
28	pixel 3 X4	pixel 7 X0	pixel 14 X0	pixel 28
27	pixel 3 X3	pixel 6 X3	pixel 13 X1	pixel 27
26	pixel 3 X2	pixel 6 X2	pixel 13 X0	pixel 26
25	pixel 3 X1	pixel 6 X1	pixel 12 X1	pixel 25
24	pixel 3 X0	pixel 6 X0	pixel 12 X0	pixel 24
23	pixel 2 X7	pixel 5 X3	pixel 11 X1	pixel 23
22	pixel 2 X6	pixel 5 X2	pixel 11 X0	pixel 22
21	pixel 2 X5	pixel 5 X1	pixel 10 X1	pixel 21
20	pixel 2 X4	pixel 5 X0	pixel 10 X0	pixel 20
19	pixel 2 X3	pixel 4 X3	pixel 9 X1	pixel 19
18	pixel 2 X2	pixel 4 X2	pixel 9 X0	pixel 18
17	pixel 2 X1	pixel 4 X1	pixel 8 X1	pixel 17
16	pixel 2 X0	pixel 4 X0	pixel 8 X0	pixel 16
15	pixel 1 X7	pixel 3 X3	pixel 7 X1	pixel 15
14	pixel 1 X6	pixel 3 X2	pixel 7 X0	pixel 14
13	pixel 1 X5	pixel 3 X1	pixel 6 X1	pixel 13
12	pixel 1 X4	pixel 3 X0	pixel 6 X0	pixel 12
11	pixel 1 X3	pixel 2 X3	pixel 5 X1	pixel 11
10	pixel 1 X2	pixel 2 X2	pixel 5 X0	pixel 10
9	pixel 1 X1	pixel 2 X1	pixel 4 X1	pixel 9
8	pixel 1 X0	pixel 2 X0	pixel 4 X0	pixel 8
7	pixel 0 X7	pixel 1 X3	pixel 3 X1	pixel 7
6	pixel 0 X6	pixel 1 X2	pixel 3 X0	pixel 6
5	pixel 0 X5	pixel 1 X1	pixel 2 X1	pixel 5
4	pixel 0 X4	pixel 1 X0	pixel 2 X0	pixel 4
3	pixel 0 X3	pixel 0 X3	pixel 1 X1	pixel 3
2	pixel 0 X2	pixel 0 X2	pixel 1 X0	pixel 2
1	pixel 0 X1	pixel 0 X1	pixel 0 X1	pixel 1
0	pixel 0 X0	pixel 0 X0	pixel 0 X0	pixel 0

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