Two tile sites (supports ARM Core Tiles and Logic Tiles)

Field Programmable Gate-Array (FPGA) that implements a bus matrix, configuration interface, peripheral controllers, and interface logic

An 8MB configuration flash that holds FPGA images

256MB of 32-bit wide DDR SDRAM

4MB of 16-bit wide Cellular (Pseudo-static) RAM

64MB of 32-bit wide NOR flash

64MB of 16-bit wide NAND Disk-on-Chip flash

up to 320MB (5x64MB) of static memory (flash or RAM) in an optional PISMO expansion board

PCI expansion connector

USB interface controller IC and connector

Ethernet interface controller IC and connector

connectors for VGA, color LCD display interface board, four UARTs, GPIO, keyboard, mouse, Smart Card, audio, MMC, and SSP

Electronic switches that select between the controllers located in the FPGA or on one of the tile sites.

debug and test connectors for JTAG, Integrated Logic Analyzer, and Trace port

general purpose DIP switches and LEDs

2 row by 16 character LCD display

power supply circuitry

Real-Time Clock (RTC)

time of year clock with backup battery

programmable clock generators.