RealView™ Emulation Baseboard User Guide

HBI-0140 Rev C

Table of Contents

About this document
Intended audience
Typographical conventions
Further reading
Feedback on the baseboard
Feedback on this document
1. Introduction
1.1. About the baseboard
1.2. Baseboard architecture
1.2.1. System architecture
1.2.2. Baseboard FPGA
1.2.3. Core Tile expansion
1.2.4. PCI expansion bus
1.2.5. Displays
1.2.6. Logic Tile expansion
1.2.7. Endianess
1.2.8. Clock generators
1.2.9. Debug and test interfaces
1.3. Tile interconnections
1.4. Precautions
1.4.1. Ensuring safety
1.4.2. Preventing damage
2. Getting Started
2.1. Setting up the baseboard
2.2. Setting the configuration switches
2.2.1. Boot memory and clock speed configuration switch S8
2.2.2. FPGA image select switch
2.2.3. Boot Monitor configuration switch
2.2.4. Config switch
2.3. Connecting a Core Tile
2.3.1. Tile status messages displayed on the LCD
2.4. Connecting a Logic Tile
2.5. Connecting expansion memory
2.6. Connecting JTAG debugging equipment
2.7. Connecting Trace
2.7.1. About trace
2.7.2. Connecting the Trace Port Analyzer to the baseboard
2.8. Supplying power
2.9. Loading FPGA and PLD images
2.9.1. Board files
2.9.2. The progcards utilities
2.9.3. Upgrading your hardware
2.9.4. Troubleshooting
2.10. Using the baseboard Boot Monitor and platform library
2.10.1. Boot Monitor configuration switches
2.10.2. Running the Boot Monitor
2.10.3. Loading Boot Monitor into NOR flash
2.10.4. Loading Boot Monitor into Disk-on-Chip
2.10.5. Using the Disk-on-Chip configure utility program
2.10.6. Redirecting character output to hardware devices
2.10.7. Using a boot script to run an image automatically
2.10.8. Rebuilding the Boot Monitor or platform library
2.10.9. Building an application with the platform library
2.10.10. Building an application that uses semihosting
2.10.11. Loading and running an application from NOR flash
2.10.12. Running an image from Disk-on-Chip
2.10.13. Using the Network Flash Utility
3. Hardware Description
3.1. Tile headers and signal interconnects
3.1.1. Buses
3.1.2. Header interconnect switches
3.2. FPGA
3.2.1. FPGA configuration
3.3. Reset logic
3.3.1. Reset and reconfiguration logic
3.3.2. Reset signals
3.3.3. Power-on reset timing
3.3.4. Memory aliasing at reset
3.4. Power supply
3.5. Memory controllers
3.6. Clock architecture
3.6.1. Tile clocks
3.6.2. Peripheral clocks
3.6.3. ICS307 programmable clock generators
3.7. Advanced Audio CODEC Interface, AACI
3.8. Character LCD controller
3.9. CLCDC interface
3.10. DMA
3.11. Ethernet interface
3.11.1. About the SMSC LAN91C111
3.12. GPIO interface
3.13. Interrupts
3.14. Keyboard/Mouse Interface, KMI
3.15. Multimedia Card Interface, MCI
3.15.1. MMC or SD operation
3.15.2. Card insertion and removal
3.15.3. Card interface description
3.16. PCI interface
3.17. Two-wire serial bus interface
3.18. Smart Card interface, SCI
3.19. Synchronous Serial Port, SSP
3.20. User switches and LEDs
3.21. UART interface
3.22. USB interface
3.23. Test, configuration, and debug interfaces
3.23.1. JTAG and USB debug port support
3.23.2. Integrated Logic Analyzer
3.23.3. Embedded trace support
4. Programmer’s Reference
4.1. Memory map
4.2. Configuration and initialization
4.2.1. Remapping of boot memory
4.2.2. Memory characteristics
4.3. Status and system control registers
4.3.1. ID Register, SYS_ID
4.3.2. Switch Register, SYS_SW
4.3.3. LED Register, SYS_LED
4.3.4. Oscillator registers, SYS_OSCx
4.3.5. Lock Register, SYS_LOCK
4.3.6. 100Hz Counter, SYS_100HZ
4.3.8. Flag registers, SYS_FLAGx and SYS_NVFLAGx
4.3.9. PCI Control Register, SYS_PCICTL
4.3.10. MCI Register, SYS_MCI
4.3.11. Flash Control Register, SYS_FLASH
4.3.12. CLCD Control Register, SYS_CLCD
4.3.13. 2.2 inch LCD Control Register SYS_CLCDSER
4.3.14. Boot select switch, SYS_BOOTCS
4.3.15. 24MHz Counter, SYS_24MHZ
4.3.16. Miscellaneous flags, SYS_MISC
4.3.17. DMA peripheral map registers, SYS_DMAPSRx
4.3.18. Peripheral I/O select, SYS_IOSEL
4.3.19. SYS_PLDCTL[2:1]
4.3.20. Bus ID register, SYS_BUSID
4.3.21. Processor ID registers, SYS_PROCID[1:0]
4.3.22. Oscillator reset registers, SYS_OSCRESETx
4.3.23. SYS_VOLTAGE[7:0]
4.3.24. Oscillator test registers, SYS_TEST_OSCx
4.3.25. SYS_GPIO
4.4. Advanced Audio CODEC Interface, AACI
4.4.1. PrimeCell Modifications
4.5. Character LCD display
4.6. Color LCD Controller, CLCDC
4.6.1. Display resolutions and display memory organization
4.7. Debug Access Port ROM table
4.8. Direct Memory Access Controller
4.9. Dynamic Memory Controller, DMC
4.9.1. Register values
4.10. Ethernet
4.11. General Purpose Input/Output, GPIO
4.11.1. Onboard I/O control
4.12. Interrupt controllers
4.12.1. Interrupt controller registers
4.12.2. Interrupt signals
4.12.3. Handling interrupts
4.13. Keyboard and Mouse Interface, KMI
4.14. MultiMedia Card Interface, MCI
4.15. PCI controller
4.15.1. Control registers
4.15.2. PCI configuration
4.16. Real Time Clock, RTC
4.17. Two-wire serial bus interface
4.18. Smart Card Interface, SCI
4.19. Synchronous Serial Port, SSP
4.20. Static Memory Controller, SMC
4.20.1. Register values
4.21. System Controller
4.21.1. PrimeCell modifications
4.22. Timers
4.23. UART
4.23.1. PrimeCell Modifications
4.24. USB interface
4.25. Watchdog
A. Signal Descriptions
A.1. Audio CODEC interface
A.2. CLCD display interface
A.3. Ethernet interface
A.4. GPIO interface
A.5. Keyboard and mouse interface
A.6. MMC and SD flash card interface
A.7. PCI connector
A.8. PISMO connector
A.8.1. Expansion connector
A.9. Smart Card interface
A.10. Synchronous Serial Port interface
A.11. Test and debug connections
A.11.1. Overview of test points
A.11.2. JTAG
A.11.3. USB debug port
A.11.4. Trace connector pinout
A.11.5. Integrated Logic Analyzer
A.12. Tile header connectors
A.12.1. HDRX signals
A.12.2. HDRY signals
A.12.3. HDRZ
A.13. UART interface
A.14. USB interface
A.15. VGA display interface
B. Specifications
B.1. Electrical specification
B.1.1. Bus interface characteristics
B.1.2. Current requirements
B.2. Clock frequency restrictions
B.3. Mechanical details
C. LCD Kits
C.1. About the CLCD display and adaptor board
C.2. Installing the CLCD display
C.2.1. Configuration
C.2.2. LCD power control
C.3. Touchscreen controller interface
C.3.1. Touchscreen interface architecture
C.3.2. Touchscreen controller programmer’s interface
C.4. Connectors
C.4.1. Interface connector
C.4.2. LCD prototyping connector
C.4.3. Touchscreen prototyping connector
C.4.4. Inverter prototyping connector
C.4.5. A/D and keypad connector
C.5. Mechanical layout
D. PCI Backplane and Enclosure
D.1. Connecting the baseboard to the PCI enclosure
D.1.1. Setting the backplane configuration switches
D.1.2. Connecting two baseboard boards
D.2. Backplane hardware
D.2.1. JTAG signals
D.3. Connectors
D.3.1. Power connector
D.3.2. Logic analyzer connector
D.3.3. JTAG connector
D.3.4. PCI connector
E. PISMO Memory Expansion Boards
E.1. About memory expansion
E.1.1. Operation without expansion memory
E.1.2. Memory board configuration
E.1.3. Fitting a memory board
E.2. Mechanical layout

List of Figures

1.1. baseboard layout
1.2. baseboard block diagram
1.3. Example of bus routing
2.1. Location of configuration switches
2.2. CONFIG slide switch
2.3. Core Tile mounted on tile site 1
2.4. Multiprocessor system with two Core Tiles
2.5. Logic Tile mounted in tile site 2
2.6. Adding PISMO memory
2.7. CONFIG slide switch
2.8. JTAG connection for debugger
2.9. Trace connection with RealView Trace
2.10. Trace connection with Multi-Trace
2.11. Power connectors
2.12. USB debug port connection for progcards_usb
3.1. Example of an AHB bus interface
3.2. Example of a multiplexed AXI bus interface
3.3. AXI multiplex timing
3.4. Core Tile in site 1
3.5. Core tile in site 1 and Logic Tile in site 2
3.6. Dual Core Tile system
3.7. Header Z routing switches
3.8. HDRZ switches for CLCDC
3.9. HDRZ switches for peripherals
3.10. FPGA block diagram
3.11. FPGA configuration
3.12. Baseboard reset logic
3.13. Power-on reset and configuration timing
3.14. JTAG and system reset
3.15. Boot memory remap logic
3.16. Power-supply regulators and protection circuitry
3.17. Reverse-polarity protection and shutdown circuit
3.18. Static memory devices
3.19. Ethernet device on static memory bus
3.20. USB device on static memory bus
3.21. Dynamic memory bus
3.22. Clock architecture
3.23. Tile clocks
3.24. Serial data and SYS_OSCx register format
3.25. Audio interface
3.26. Character display
3.27. Display interface
3.28. DMA channels
3.29. Ethernet interface architecture
3.30. GPIO block diagram
3.31. Interrupt controllers for tile site 1 and 2
3.32. KMI block diagram
3.33. MCI interface
3.34. PCI bridge
3.35. Serial bus block diagram
3.36. SCI block diagram
3.37. SSP block diagram
3.38. Switch and LED interface
3.39. UARTs block diagram
3.40. UART0 interface
3.41. Simplified interface for UART[3:1]
3.42. ISP1761 block diagram
3.43. External connection to ground for nICEDETECT signal
3.44. JTAG signal routing
3.45. JTAG signal routing in config mode
3.46. JTAG signal routing in debug mode
4.1. System memory map for standard peripherals
4.2. ID Register, SYS_ID
4.3. SYS_SW
4.4. SYS_LED
4.5. Oscillator Register, SYS_OSCx
4.6. Lock Register, SYS_LOCK
4.7. SYS_MCI
4.10. SYS_MISC register
4.11. DMA mapping register
4.13. SYS_BUSID register
4.14. Processor ID registers
4.15. Oscillator Register, SYS_OSCRESETx
4.16. AACI ID register
4.17. DMC register overview
4.18. Baseboard to PCI mapping
4.19. PCI_IMAPx register
4.20. PCI_SELFID register
4.21. PCI_FLAGS register
4.22. PCI to baseboard mapping
4.23. memory remap register
4.24. I/O remap register
A.1. Audio connectors
A.2. CLCD Interface connector J4
A.3. Ethernet connector J44
A.4. GPIO connector J9
A.5. KMI connector J22 and J23
A.6. MMC/SD card socket pin numbering, J21
A.7. MultiMedia Card (MMC)
A.8. Samtec connector
A.9. Smart Card contacts assignment
A.10. J30 SCI expansion connector J30
A.11. SSP expansion interface, J32
A.12. Test points and test connectors
A.13. Links
A.14. Switches and indicators
A.15. JTAG connector J18
A.16. USB debug connector J16
A.17. AMP Mictor connector
A.18. Integrated logic analyzer connector J19
A.19. HDRX, HDRY, and HDRZ pin numbering
A.20. Serial connector
A.21. USB interfaces
A.22. VGA connector J5
B.1. Baseboard mechanical details
B.2. Baseboard mounting holes
C.1. CLCD adaptor board connectors (bottom view)
C.2. Small CLCD enclosure
C.3. Large CLCD enclosure
C.4. Displays mounted directly onto top of adaptor board.
C.5. CLCD adaptor board connection
C.6. CLCD buffer and power supply control links
C.7. Touchscreen and keypad interface
C.8. Touchscreen resistive elements
C.9. CLCD adaptor board mechanical layout
D.1. Installing the platform board into the PCI enclosure
D.2. PCI backplane interrupt routing
D.3. Multiple boards on PCI bus
D.4. PCI backplane
D.5. JTAG signal flow on the PCI backplane
D.6. AMP Mictor connector J4
D.7. PCI expansion board JTAG connector J5
E.1. Static memory board block diagram
E.2. Static memory board layout

List of Tables

2.1. Selecting the boot device
2.2. Default switch positions
2.3. Default positions for FPGA select switch S10
2.4. Default positions for FPGA select switch S10
2.5. Tile status messages displayed on character LCD
2.6. STDIO redirection
2.7. Boot Monitor commands
2.8. Boot Monitor Configure commands
2.9. Boot Monitor Debug commands
2.10. Boot Monitor NOR flash commands
2.11. Configure utility commands
2.12. Platform library options
2.13. NFU commands
2.14. NFU MANAGE commands
3.1. AXI multiplexor timing
3.2. Bus usage on tile sites
3.3. Reset sources
3.4. Reset and configuration signals
3.5. Devices on the static memory bus
3.6. Clock signals on tiles
3.7. baseboard clocks and clock control signals
3.8. Audio system specification
3.9. AC’97 audio debug signals on J3
3.10. Display interface signals
3.11. DMA signals for external devices
3.12. Ethernet signals
3.13. MMC/SD interface signals
3.14. MMC signals
3.15. Serial bus addresses
3.16. Two-wire serial bus signals
3.17. Smart Card interface signals
3.18. SSP signal descriptions
3.19. Serial interface signal assignment
3.20. USB interface signal assignment
3.21. JTAG related signals
4.1. System memory map
4.2. Memory map for standard peripherals
4.3. Boot memory
4.4. Memory chip selects and address range
4.5. Register map for system control registers
4.6. ID Register, SYS_ID bit assignment
4.7. Oscillator Register, SYS_OSCx bit assignment
4.8. Lock Register, SYS_LOCK bit assignment
4.9. Init register 1, SYS_CONFIGDATA1 bit assignment
4.10. Init register 2, SYS_CONFIGDATA2 bit assignment
4.11. Flag registers
4.12. PCI control
4.13. MCI control
4.14. Flash control
4.15. SYS_CLCD register
4.16. SYS_CLCDSER register
4.17. SYS_BOOTCS register
4.18. SYS_MISC register
4.19. DMA map registers
4.20. SYS_DMAPx, DMA mapping register format
4.21. Peripheral select signals
4.22. Peripheral routing signals
4.23. Core PLD control register, SYS_PLDCTL bit assignment
4.24. Bus ID
4.25. Processor ID
4.26. SYS_VOLTAGE register
4.27. Oscillator test registers
4.28. Interrupt test
4.29. AACI implementation
4.30. Modified AACI PeriphID3 register
4.31. Character LCD display implementation
4.32. Character LCD control and data registers
4.33. Character LCD display commands
4.34. CLCDC implementation
4.35. Values for different display resolutions
4.36. Assignment of display memory to R[7:0], G[7:0], and B[7:0]
4.37. Assignment of display memory for 8, 4, 2, and 1 bits per pixel
4.38. Assignment of display memory to pixels
4.39. DMAC implementation
4.40. DMA channel allocation
4.41. DMC implementation
4.42. DMC register summary
4.43. Ethernet implementation
4.44. GPIO implementation
4.45. GPIO2 and MCI status signals
4.46. Generic Interrupt Controller implementation
4.47. GIC interface registers
4.48. GIC distribution registers
4.49. Interrupt signals to controllers
4.50. KMI implementation
4.51. MCI implementation
4.52. PCI controller implementation
4.53. PCI bus memory map
4.54. PCI controller registers
4.55. PCI_IMAPx register format
4.56. PCI_SELFID register format
4.57. PCI_FLAGS register format
4.58. memory remap register format
4.59. I/O remap register format
4.60. PCI backplane configuration header addresses (self-config)
4.61. PCI backplane configuration header addresses (normal configuration)
4.62. PCI configuration space header
4.63. PCI bus commands supported
4.64. RTC implementation
4.65. Serial bus implementation
4.66. Serial bus register
4.67. Serial bus device addresses
4.68. SCI implementation
4.69. SSP implementation
4.70. SSMC implementation
4.71. Register values for PISMO CS0 (SMC CS4)
4.72. System controller implementation
4.73. SYS_CTRL register
4.74. Timer implementation
4.75. UART implementation
4.76. USB implementation
4.77. USB controller base address
4.78. Watchdog implementation
A.1. Audio connectors
A.2. CLCD Interface board connector J4
A.3. Ethernet signals
A.4. Mouse and keyboard port signal descriptions
A.5. MultiMedia Card interface signals
A.6. PCI connectors
A.7. Samtec part numbers
A.8. Memory connector signals
A.9. Smart Card connector signal assignment
A.10. Signals on expansion connector
A.11. SSP signal assignment
A.12. Test point functions
A.13. Links
A.14. Indicators
A.15. Switches
A.16. JTAG signals
A.17. Trace connector J49
A.18. Trace connector J50
A.19. Samtec part numbers
A.20. HDRX signals
A.21. HDRY signals
A.22. HDRZ signals
A.23. Serial plug signal assignment
A.24. VGA connector signals
B.1. baseboard electrical characteristics
B.2. Current requirements (from 12V DC IN)
B.3. Typical current loading on baseboard supplies
C.1. Displays available with adaptor board
C.2. Power configuration
C.3. Touchscreen host interface signal assignment
C.4. CLCD interface connector J2
C.5. LCD prototyping connector J1
C.6. Touchscreen prototyping connector J3
C.7. Inverter prototyping connector J4
C.8. A/D and keypad J13
D.1. LED indicators
D.2. Configuration switches
D.3. Power and reset switches
D.4. Test points
D.5. ATX power connector
D.6. Mictor connector pinout J4
D.7. PCI connectors
E.1. Memory width encoding

Proprietary Notice

Words and logos marked with® or ™ are registered trademarks or trademarks owned by ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The baseboard generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the board

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help


It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision ADecember 2005New document
Revision BJuly 2006Second release to fix documentation defects
Revision CMay 2007Third release to fix documentation defects
Revision DOctober 2007Fourth release to fix documentation defects
Revision EApril 2011Fifth release to fix documentation defects
Copyright © 2005-2011 ARM Limited. All rights reserved.ARM DUI 0303E