4.1. Write address channel checks

Table 4.1 lists the write address channel checking rules.

Table 4.1. Write address channel checking rules

AssertionDescription

Specification reference

AXI_ERRM_AWID_STABLEAWID must remain stable when AWVALID is asserted and AWREADY is LOWHandshake process on Page 3-2
AXI_ERRM_AWID_XA value of X on AWID is not permitted when AWVALID is HIGHWrite address channel on Page 3-3
AXI_ERRM_AWADDR_BOUNDARYA write burst cannot cross a 4KB boundaryAbout addressing options on Page 4-2
AXI_ERRM_AWADDR_WRAP_ALIGNA write transaction with burst type WRAP has an aligned addressWrapping burst on Page 4-6
AXI_ERRM_AWADDR_STABLEAWADDR remains stable when AWVALID is asserted and AWREADY is LOWHandshake process on Page 3-2
AXI_ERRM_AWADDR_XA value of X on AWADDR is not permitted when AWVALID is HIGHWrite address channel on Page 3-3
AXI_ERRM_AWLEN_WRAPA write transaction with burst type WRAP has a length of 2, 4, 8, or 16Wrapping burst on Page 4-6
AXI_ERRM_AWLEN_STABLEAWLEN remains stable when AWVALID is asserted and AWREADY is LOWHandshake process on Page 3-2
AXI_ERRM_AWLEN_XA value of X on AWLEN is not permitted when AWVALID is HIGHWrite address channel on Page 3-3
AXI_ERRM_AWSIZE_STABLEAWSIZE remains stable when AWVALID is asserted and AWREADY is LOWHandshake process on Page 3-2
AXI_ERRM_AWSIZEThe size of a write transfer does not exceed the width of the data interfaceBurst size on Page 4-4
AXI_ERRM_AWSIZE_XA value of X on AWSIZE is not permitted when AWVALID is HIGHWrite address channel on Page 3-3
AXI_ERRM_AWBURSTA value of 2’b11 on AWBURST is not permitted when AWVALID is HIGHTable 4-3 on Page 4-5
AXI_ERRM_AWBURST_STABLEAWBURST remains stable when AWVALID is asserted and AWREADY is LOWHandshake process on Page 3-2
AXI_ERRM_AWBURST_XA value of X on AWBURST is not permitted when AWVALID is HIGHWrite address channel on Page 3-3
AXI_ERRM_AWLOCKA value of 2'b11 on AWLOCK is not permitted when AWVALID is HIGHTable 6-1 on Page 6-2
AXI_ERRM_AWLOCK_ENDA master must wait for an unlocked transaction at the end of a locked sequence to complete before issuing another write addressLocked access on Page 6-7
AXI_ERRM_AWLOCK_IDA sequence of locked transactions must use a single IDLocked access on Page 6-7
AXI_ERRM_AWLOCK_LASTA master must wait for all locked transactions to complete before issuing an unlocked write addressLocked access on Page 6-7
AXI_ERRM_AWLOCK_STABLEAWLOCK remains stable when AWVALID is asserted and AWREADY is LOWHandshake process on Page 3-2
AXI_ERRM_AWLOCK_STARTA master must wait for all outstanding transactions to complete before issuing a write address that is the first in a locked sequenceLocked access on Page 6-7
AXI_ERRM_AWLOCK_XA value of X on AWLOCK is not permitted when AWVALID is HIGHWrite address channel on Page 3-3
AXI_RECM_AWLOCK_BOUNDARYRecommended that all locked transaction sequences remain within the same 4KB address regionLocked access on Page 6-7
AXI_RECM_AWLOCK_CTRLRecommended that a master must not change AWPROT or AWCACHE during a sequence of locked accessesLocked access on Page 6-7
AXI_RECM_AWLOCK_NUMRecommended that locked transaction sequences are limited to two transactionsLocked access on Page 6-7
AXI_ERRM_AWCACHEWhen AWVALID is HIGH and AWCACHE[1] is LOW then AWCACHE[3:2] are also LOWTable 5-1 on Page 5-3
AXI_ERRM_AWCACHE_STABLEAWCACHE remains stable when AWVALID is asserted and AWREADY is LOWHandshake process on Page 3-2
AXI_ERRM_AWCACHE_XA value of X on AWCACHE is not permitted when AWVALID is HIGHWrite address channel on Page 3-3
AXI_ERRM_AWPROT_STABLEAWPROT remains stable when AWVALID is asserted and AWREADY is LOWHandshake process on Page 3-2
AXI_ERRM_AWPROT_XA value of X on AWPROT is not permitted when AWVALID is HIGHWrite address channel on Page 3-3
AXI_ERRM_AWVALID_RESETAWVALID is LOW for the first cycle after ARESETn goes HIGHReset on Page 11-2
AXI_ERRM_AWVALID_STABLEWhen AWVALID is asserted then it remains asserted until AWREADY is HIGHWrite address channel on Page 3-3
AXI_ERRM_AWVALID_XA value of X on AWVALID is not permitted when not in reset-
AXI_ERRS_AWREADY_XA value of X on AWREADY is not permitted when not in reset-
AXI_RECS_AWREADY_MAX_WAITRecommended that AWREADY is asserted within MAXWAITS cycles of AWVALID being asserted-

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