4.2. Write data channel checks

Table 4.2 lists the write data channel checking rules.

Table 4.2. Write data channel checking rules

AssertionDescription

Specification reference

AXI_ERRM_WID_STABLEWID remains stable when WVALID is asserted and WREADY is LOW.Handshake process on Page 3-2
AXI_ERRM_WID_XA value of X on WID is not permitted when WVALID is HIGH.Write data channel on Page 3-4
AXI_ERRM_WDATA_NUM

The number of write data items matches AWLEN for the corresponding address. This is triggered when any of the following occurs:

  • write data arrives and WLAST set and the WDATA count is not equal to AWLEN

  • write data arrives and WLAST not set and the WDATA count is equal to AWLEN

  • ADDR arrives, WLAST already received, and the WDATA count is not equal to AWLEN.

Table 4-1 on Page 4-3
AXI_ERRM_WDATA_ORDERThe order in which addresses and the first write data item are produced must match.Write data interleaving on Page 8-6
AXI_ERRM_WDATA_STABLEWDATA remains stable when WVALID is asserted and WREADY is LOW.Handshake process on Page 3-2
AXI_ERRM_WDATA_XA value of X on WDATA is not permitted when WVALID is HIGH.-
AXI_ERRM_WSTRB

Write strobes must only be asserted for the correct byte lanes as determined from the:

  • start address

  • transfer size

  • beat number.

Write strobes on Page 9-3
AXI_ERRM_WSTRB_STABLEWSTRB remains stable when WVALID is asserted and WREADY is LOW.Handshake process on Page 3-2
AXI_ERRM_WSTRB_XA value of X on WSTRB is not permitted when WVALID is HIGH.-
AXI_ERRM_WLAST_STABLEWLAST remains stable when WVALID is asserted and WREADY is LOW.Handshake process on Page 3-2
AXI_ERRM_WLAST_XA value of X on WLAST is not permitted when WVALID is HIGH.-
AXI_ERRM_WVALID_RESETWVALID is LOW for the first cycle after ARESETn goes HIGH.Reset on Page 11-2
AXI_ERRM_WVALID_STABLEWhen WVALID is asserted then it must remain asserted until WREADY is HIGH.Write data channel on Page 3-4
AXI_ERRM_WVALID_XA value of X on WVALID is not permitted when not in reset.-
AXI_RECS_WREADY_MAX_WAITRecommended that WREADY is asserted within MAXWAITS cycles of WVALID being asserted.-
AXI_ERRS_WREADY_XA value of X on WREADY is not permitted when not in reset.-
AXI_ERRM_WDEPTHA master can interleave a maximum of WDEPTH write data bursts.Write data interleaving on Page 8-6

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