4.4. Read address channel checks

Table 4.4 lists the read address channel checking rules.

Table 4.4. Read address channel checking rules

AssertionDescription

Specification reference

AXI_ERRM_ARID_STABLEARID remains stable when ARVALID is asserted and ARREADY is LOWHandshake process on Page 3-2
AXI_ERRM_ARID_XA value of X on ARID is not permitted when ARVALID is HIGHRead address channel on Page 3-4
AXI_ERRM_ARADDR_BOUNDARYA read burst cannot cross a 4KB boundaryAbout addressing options on Page 4-2
AXI_ERRM_ARADDR_STABLEARADDR remains stable when ARVALID is asserted and ARREADY is LOWHandshake process on Page 3-2
AXI_ERRM_ARADDR_WRAP_ALIGNA read transaction with a burst type of WRAP must have an aligned addressWrapping burst on Page 4-6
AXI_ERRM_ARADDR_XA value of X on ARADDR is not permitted when ARVALID is HIGHRead address channel on Page 3-4
AXI_ERRM_ARLEN_STABLEARLEN remains stable when ARVALID is asserted and ARREADY is LOWHandshake process on Page 3-2
AXI_ERRM_ARLEN_WRAPA read transaction with burst type of WRAP must have a length of 2, 4, 8, or 16Wrapping burst on Page 4-6
AXI_ERRM_ARLEN_XA value of X on ARLEN is not permitted when ARVALID is HIGHRead address channel on Page 3-4
AXI_ERRM_ARSIZEThe size of a read transfer must not exceed the width of the data interfaceBurst size on Page 4-4
AXI_ERRM_ARSIZE_STABLEARSIZE remains stable when ARVALID is asserted and ARREADY is LOWHandshake process on Page 3-2
AXI_ERRM_ARSIZE_XA value of X on ARSIZE is not permitted when ARVALID is HIGHRead address channel on Page 3-4
AXI_ERRM_ARBURSTA value of 2'b11 on ARBURST is not permitted when ARVALID is HIGHTable 4-3 on Page 4-5
AXI_ERRM_ARBURST_STABLEARBURST remains stable when ARVALID is asserted and ARREADY is LOWHandshake process on Page 3-2
AXI_ERRM_ARBURST_XA value of X on ARBURST is not permitted when ARVALID is HIGHRead address channel on Page 3-4
AXI_ERRM_ARLOCKA value of 2'b11 on ARLOCK is not permitted when ARVALID is HIGHTable 6-1 on Page 6-2
AXI_ERRM_ARLOCK_ENDA master must wait for an unlocked transaction at the end of a locked sequence to complete before issuing another read addressLocked access on Page 6-7
AXI_ERRM_ARLOCK_IDA sequence of locked transactions must use a single IDLocked access on Page 6-7
AXI_ERRM_ARLOCK_LASTA master must wait for all locked transactions to complete before issuing an unlocked read addressLocked access on Page 6-7
AXI_ERRM_ARLOCK_STABLEARLOCK remains stable when ARVALID is asserted and ARREADY is LOWHandshake process on Page 3-2
AXI_ERRM_ARLOCK_STARTA master must wait for all outstanding transactions to complete before issuing a read address that is the first in a locked sequenceLocked access on Page 6-7
AXI_ERRM_ARLOCK_XA value of X on ARLOCK is not permitted when ARVALID is HIGHRead address channel on Page 3-4
AXI_RECM_ARLOCK_BOUNDARYRecommended that all locked transaction sequences are kept within the same 4KB address regionLocked access on Page 6-7
AXI_RECM_ARLOCK_CTRLRecommended that a master must not change ARPROT or ARCACHE during a sequence of locked accessesLocked access on Page 6-7
AXI_RECM_ARLOCK_NUMRecommended that locked transaction sequences are limited to two transactionsLocked access on Page 6-7
AXI_ERRM_ARCACHEWhen ARVALID is HIGH, if ARCACHE[1] is LOW then ARCACHE[3:2] must also be LOWTable 5-1 on Page 5-3
AXI_ERRM_ARCACHE_STABLEARCACHE remains stable when ARVALID is asserted and ARREADY is LOWHandshake process on Page 3-2
AXI_ERRM_ARCACHE_XA value of X on ARCACHE is not permitted when ARVALID is HIGHRead address channel on Page 3-4
AXI_ERRM_ARPROT_STABLEARPROT remains stable when ARVALID is asserted and ARREADY is LOWHandshake process on Page 3-2
AXI_ERRM_ARPROT_XA value of X on ARPROT is not permitted when ARVALID is HIGHRead address channel on Page 3-4
AXI_ERRM_ARVALID_RESETARVALID is LOW for the first cycle after ARESETn goes HIGHReset on Page 11-2
AXI_ERRM_ARVALID_STABLEWhen ARVALID is asserted then it remains asserted until ARREADY is HIGHRead address channel on Page 3-4
AXI_ERRM_ARVALID_XA value of X on ARVALID is not permitted when not in reset-
AXI_ERRS_ARREADY_XA value of X on ARREADY is not permitted when not in reset-
AXI_RECS_ARREADY_MAX_WAITRecommended that ARREADY is asserted within MAXWAITS cycles of ARVALID being asserted-

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