4.3. Write response channel checks

Table 4.3 lists the write response channel checking rules.

Table 4.3. Write response channel checking rules

AssertionDescription

Specification reference

AXI_ERRS_BID_STABLEBID remains stable when BVALID is asserted and BREADY is LOWHandshake process on Page 3-2
AXI_ERRS_BID_XA value of X on BID is not permitted when BVALID is HIGH-
AXI_ERRS_BRESPA slave must only give a write response after the last write data item is transferredDependencies between channel handshake signals on Page 3-7
AXI_ERRS_BRESP_ALL_DONE_EOSAll write transaction addresses are matched with a corresponding buffered response-
AXI_ERRS_BRESP_EXOKAYAn EXOKAY write response can only be given to an exclusive write accessExclusive access from the perspective of the slave on Page 6-4
AXI_ERRS_BRESP_STABLEBRESP remains stable when BVALID is asserted and BREADY is LOWHandshake process on Page 3-2
AXI_ERRS_BRESP_XA value of X on BRESP is not permitted when BVALID is HIGHWrite response channel on Page 3-4
AXI_ERRS_BVALID_RESETBVALID is LOW for the first cycle after ARESETn goes HIGHReset on Page 11-2
AXI_ERRS_BVALID_STABLEWhen BVALID is asserted then it must remain asserted until BREADY is HIGHWrite response channel on Page 3-4
AXI_ERRS_BVALID_XA value of X on BVALID is not permitted when not in reset-
AXI_RECM_BREADY_MAX_WAITRecommended that BREADY is asserted within MAXWAITS cycles of BVALID being asserted-
AXI_ERRM_BREADY_XA value of X on BREADY is not permitted when not in reset-
AXI_RECS_BRESPA slave must not give a write response before the write addresshttp://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.faqs/11424.html

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