1.2. Tools

The protocol checker is supplied as either:

Verilog OVL

A standard for defining, reporting and parameterizing assertions. OVL assertions are predefined assertions standardized by the Accellera committee. They are free to use and download. You can obtain them and more information from http://www.eda.org/ovl/.

The protocol checker supports the standard OVL defines from Accellera, v2.3 (09 June 2008).

The protocol checker is backward compatible with older versions of the Accellera OVL Library. To use the April 2003 version of the library, set the following define:

`define AXI_USE_OLD_OVL
SystemVerilog

A Hardware Description and Verification Language (HDVL) standard that extends the established Verilog language. It was developed to improve productivity in the design of large gate count, IP-based, bus-intensive chips. SystemVerilog is targeted at the chip implementation and verification flow, with links to the system level design flow.

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