A.1. RDATA stable failure

Figure A.1 shows the timing diagram for a failure of the AXI_ERRS_RDATA_STABLE check.

Figure A.1. RDATA stable failure


RDATA changes at T7 when RVALID is HIGH and RREADY is LOW. The protocol checker samples the change at T8.

Example A.1 shows the protocol checker transcript for this failure.

Example A.1. RDATA stable failure

# Loading work.TB
# Loading work.AxiPC
# Loading ../ovl/work.assert_implication
# do startup.do
# OVL_ERROR : ASSERT_WIN_UNCHANGE : AXI_ERRS_RDATA_STABLE. RDATA must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2. : : severity 1 : time 250 ns : TB.uAxiPC.errs_rdata_stable.ovl_error
# OVL_ERROR  : AXI_ERRS_RDATA_STABLE. RDATA must remain stable when RVALID is asserted and RREADY low. Spec: section 3.1, and figure 3-1, on page 3-2. :  : severity 1 : time 270 ns : TB.uAxiPC.errs_rdata_stable.ovl_error
# Break at rdata_stable.v line 69
# Simulation Breakpoint: Break at rdata_stable.v line 69

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