2.3. Instantiating the protocol checker module

The protocol checker module contains the Verilog port list. Connect the AXI signals to the corresponding signals in your design.

Place the module instantiation inside `ifdef ASSERT_ON and `endif lines to disable the OVL assertions if necessary, during synthesis for example. Example Verilog file listing shows the module instantiated in a top level Verilog file inside these compiler directives.

The AXI signals are signals that the AMBA AXI Protocol v1.0 Specification describes.

The low-power interface signals are defined as weak pull-up and you can leave them unconnected if you are not using them. They are named:

The Verilog file contains checks for user-configurable sideband signals. These signals are defined as weak pull-down and you can leave them unconnected. The AMBA AXI Protocol v1.0 Specification does not support these signals.

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