2.3.1. Example Verilog file listing

Example 2.1 shows part of a design HDL file instantiating the protocol checker module. You can, if necessary, override any of the protocol checker parameters by using defparam at this level.

Example 2.1. Example Verilog file listing

`ifdef ASSERT_ON

    AxiPC u_axi_ovl
          (
          .ACLK (ACLK),
          .ARESETn (ARESETn),
          .AWID (AWID),
          .AWADDR (AWADDR),
          .AWLEN (AWLEN),
          .AWSIZE (AWSIZE),
          .AWBURST (AWBURST),
          .AWLOCK (AWLOCK),
          .AWCACHE (AWCACHE),
          .AWPROT (AWPROT),
          .AWUSER ({32{1’b0}}),
          .AWVALID (AWVALID),
          .AWREADY (AWREADY),
          .WID (WID),
          .WLAST (WLAST),
          .WDATA (WDATA),
          .WSTRB (WSTRB),
          .WUSER ({32{1’b0}}),
          .WVALID (WVALID),
          .WREADY (WREADY),
          .BID (BID),
          .BRESP (BRESP),
          .BUSER ({32{1’b0}}),
          .BVALID (BVALID),
          .BREADY (BREADY),
          .ARID (ARID),
          .ARADDR (ARADDR),
          .ARLEN (ARLEN),
          .ARSIZE (ARSIZE),
          .ARBURST (ARBURST),
          .ARLOCK (ARLOCK),
          .ARCACHE (ARCACHE),
          .ARPROT (ARPROT),
          .ARUSER ({32{1’b0}}),
          .ARVALID (ARVALID),
          .ARREADY (ARREADY),
          .RID (RID),
          .RLAST (RLAST),
          .RDATA (RDATA),
          .RRESP (RRESP),
          .RUSER ({32{1'b0}}),
          .RVALID (RVALID),
          .RREADY (RREADY),
          .CACTIVE (CACTIVE),
          .CSYSREQ (CSYSREQ),
          .CSYSACK (CSYSACK)
          );
`endif // `ifdef ASSERT_ON

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