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This section describes the interrupt modes and contains the following subsections:
Three interrupt modes are supported by the CT11MPCore, these are:
Legacy mode
Normal mode with DCC interrupt routing
Normal mode without DCC interrupt routing
To set the interrupt mode in the CT11MPCore PLD, set the appropriate
values in the INTMODE[2:0] field in the SYS_PLD_CTL1
register in the EB system FPGA.
See EB system FPGA registers for register
details.
The interrupt routing available in the different modes is shown in Figure 3.8.
A total of 16 general purpose interrupt lines are provided at header HDRZ.
The CT11MPCore PLD routing functions are:
to route the HDRZ header interrupt sources to the ARM11 MPCore test chip distributed interrupt controller inputs, INT[15:0]
set
the INTMODE[2:0] field in the SYS_PLD_CTL1 register
to bx00 to select Legacy mode interrupt
routing
set the INTMODE[2:0] field in
the SYS_PLD_CTL1 register to bx01 to select Normal
mode with DCC interrupt routing
set the INTMODE[2:0] field in
the SYS_PLD_CTL1 register to bx1x to select Normal
mode without DCC interrupt routing.
INT[15:0] on the ARM11 MPCore test chip maps to INT[47:32] in the ARM11 MPCore distributed interrupt controller. See ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for further details.
to route the CPU legacy IRQ request input lines, nIRQ[3:0], for DCC interrupt handling
The COMMRX[3:0] DCC interrupt sources are inverted by the CT11MPCore PLD.
to route the Z[215:212] pins on header HDRZ to drive the CPU legacy fast interrupt request lines, nFIQ[3:0]
set the INTMODE[2:0] field in
the SYS_PLD_CTL1 register to b1xx to enable the nFIQ[3:0] interrupt lines.
The CT11MPCore PLD inverts the Z[215:212] signals connected
to nFIQ[3:0] when INTMODE[2] is
HIGH. When INTMODE[2] is LOW, the CT11MPCore
PLD disables the nFIQ[3:0] interrupt
lines by forcing them HIGH.
The interrupt routing options, between the ARM11 MPCore test chip and the EB, are shown in Table 3.2.
Table 3.2. Interrupt routing options
| Interrupt | Legacy mode (bx00 default) | Normal mode with DCC (bx01) | Normal mode (bx1x) |
|---|---|---|---|
| INT 0 | COMMRX[0] | AACI | AACI |
| INT 1 | COMMRX[1] | EB_TIMER0/1 | EB_TIMER0/1 |
| INT 2 | COMMRX[2] | EB_TIMER2/3 | EB_TIMER2/3 |
| INT 3 | COMMRX[3] | USB | USB |
| INT 4 | COMMTX[0] | EB_UART0 | EB_UART0 |
| INT 5 | COMMTX[1] | EB_UART1 | EB_UART1 |
| INT 6 | COMMTX[2] | EB_RTC | EB_RTC |
| INT 7 | COMMTX[3] | EB_KMI0 (KYBD) | EB_KMI0 (KYBD) |
| INT 8 | EB_GIC1_nIRQ | COMMTX[0] | EB_KMI1 (MOUSE) |
| INT 9 | EB_GIC2_nIRQ | COMMTX[1] | EB_ETHINT |
| INT 10 | USB | COMMTX[2] | EB_GIC1_nIRQ |
| INT 11 | AACI | COMMTX[3] | EB_GIC2_nIRQ |
| INT 12 | EB_GIC1_nFIQ | EB_GIC1_nFIQ | EB_GIC1_nFIQ |
| INT 13 | EB_GIC2_nFIQ | EB_GIC2_nFIQ | EB_GIC2_nFIQ |
| INT 14 | MMCI0 | MMCI0 | MMCI0 |
| INT 15 | MMCI1 | MMCI1 | MMCI1 |
| nIRQ[0] | EB_GIC2_nIRQ | nCOMMRX[0] | 1 |
| nIRQ[1] | 1 | nCOMMRX[1] | 1 |
| nIRQ[2] | 1 | nCOMMRX[2] | 1 |
| nIRQ[3] | 1 | nCOMMRX[3] | 1 |
| EB_COMMRX | COMMRX[0] | 0 | 0 |
| EB_COMMTX | COMMTX[1] | 0 | 0 |
| Copyright © 2005-2010 ARM Limited. All rights reserved. | ARM DUI 0318F |
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