Core Tile for ARM11 MPCore User Guide: 3.10.3. EB system FPGA registers

3.10.3. EB system FPGA registers

The CT11MPCore specific registers implemented in the EB system FPGA are:

SYS_PLD_CTRL1

This register sets the PLD serial write data register fields

HDRZEN
MPMASTNUM
L2BYPASS
INTMODE[2:0]
DBGMUX[11:0]
nCPURESET[3:0]
CFGEND[1:0]
VINITHI[3:0]

SYS_PLD_CTRL2

This register reads the PLD serial read data register fields

COMMRX[3:0]
COMMTX[3:0]
STANDBYWFI[3:0]
SMPnAMP[3:0]
RESETREQ[3:0]
PLDVER[3:0]

SYS_PLD_INIT

This register defines the ARM11 MPCore test chip Test chip PLL control register and Test chip clock divider register hardware initialization values.

The Test chip PLL control register initialization fields are: PB[3:0] PA[3:0] N[3:0] M[3:0] PBSTBY STBY PLLEN

The Test chip clock divider register initialization fields are: CLKOUTDIV[3:0]

Note

The SYS_PLD_INIT register only loads the Test chip PLL control register and Test chip clock divider register after the EB nPB reset button is pressed.

The ARM11 MPCore test chip registers can also be accessed directly to control the PLL and clock divider once out of reset. See Clocks for details on accessing the ARM11 MPCore test chip clock control registers.

SYS_VOLTAGE0

This register reads and sets the VDDCORE voltage fields

ADC_DATA[11:0]

DAC_DATA[7:0]

SYS_VOLTAGE1

This register reads and sets the AVDD (PLL) voltage fields

ADC_DATB[11:0]

DAC_DATB[7:0]

SYS_VOLTAGE2

This register reads the VDDCORE current field

ADC_DATC[11:0]

DAC_DATC{7:0] (not used)

SYS_VOLTAGE3

This register reads the AVDD (PLL) current field

ADC_DATD[11:0]

DAC_DATD[7:0] (not used)

The EB SYS register base address, SYSBASE, is 0x10000000.

The EB system FPGA registers are listed in Table 3.8.

Table 3.8. EB system FPGA registers

Name	Address	Description
SYS_PLD_CTRL1	`0x10000074`	This register sets the PLD serial write data register fields. See SYS_PLD_CTRL1 for details.
SYS_PLD_CTRL2	`0x10000078`	This register reads the PLD serial read data register fields. See SYS_PLD_CTRL2 for details.
SYS_PLD_INIT	`0x1000007C`	This register sets the ARM11MPCore test chip Test chip PLL control register and Test chip clock divider register hardware initialization values. See SYS_PLD_INIT for details.
SYS_VOLTAGE0	`0x100000A0`	This register reads and sets the VDDCORE voltage fields. See SYS_VOLTAGE0 for details.
SYS_VOLTAGE1	`0x100000A4`	This register reads and sets the AVDD (PLL) voltage fields. See SYS_VOLTAGE1 for details.
SYS_VOLTAGE2	`0x100000A8`	This register reads the VDDCORE current field. See SYS_VOLTAGE2 for details.
SYS_VOLTAGE3	`0x100000AC`	This register reads the AVDD (PLL) current field. See SYS_VOLTAGE3 for details.

Note

All writable EB SYS registers must be unlocked first. Write 0xA05F to the SYS_LOCK register located at SYSBASE+0x20 as follows:

Address [31:0]=0x10000020, Data [15:0]=0xA05F

Once unlocked, the registers will remain unlocked until the EB is reset.

SYS_PLD_CTRL1

This register is located at SYSBASE+0x74 as follows:

Address [31:0]=0x10000074

Note

This register is locked for write by SYS_LOCK. Write 0xA05F to 0x10000020 to unlock until next EB reset.

Figure 3.15 shows the SYS_PLD_CTRL1 register bit assignments.

Figure 3.15. SYS_PLD_CTRL1 register

Table 3.9 lists the SYS_PLD_CTRL1 register bit assignments.

Table 3.9. SYS_PLD_CTRL1 register

Bits	Access	Name	Reset value	Description
[31:28]	Write ignored	−	`0x0`	reserved.
[27]	Write only Lockable	HDRZEN	`b0`	Header Z optional signal mux enable: 0: disable optional HDRZ signals 1: enable optional HDRZ signals. See HDRZ signal mux.
[26]	Write only Lockable	MPMASTNUM	`b0`	Selects the number of ARM11 MPCore test chip master ports: 0: one master port, M0. When one master is selected, master port 0 is used 1: two master ports, M0 and M1 are used. See L220 bypass module.
[25]	Write only Lockable	L2BYPASS	`b0`	Selects the L2 cache bypassing: 0: you can use the L2 cache 1: the L2 cache is bypassed. See L220 bypass module.
[24:22]	Write only Lockable	INTMODE	`b000`	Interrupt mode: bx00: Legacy bx01: New with DCC bx1x: New no DCC b1xx: FIQ[3:0] enable (independent of INTMODE[1:0]). See Interrupts.
[21:10]	Write only Lockable	DBGMUX	`0x000`	Sets the user defined debug cross-trigger mode. The required ARM11 MPCore EDBGRQ[3:0] and DBGACK[3:0] signals are routed using a debug matrix in the CT11MPCore PLD. See Debug cross-trigger matrix.
[9:6]	Write only Lockable	nCPURESET	`b1111`	Individual MPCore CPU resets. nCPURESET[x] resets CPU[x}. See Resets.
[5:4]	Write only Lockable	CFGEND	`b00`	The U and EE bits reset values in the CP15 Control Register and E Bit reset value in CPSR/SPSR depend on the value of CFGEND[1:0]. See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360).
[3:0]	Write only Lockable	VINITHI	`b0000`	When HIGH, indicates high-Vecs mode for the respective MPCore CPU. See ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360).

SYS_PLD_CTRL2

This register is located at SYSBASE+0x78 as follows:

Address [31:0]=0x10000078

Figure 3.16 shows the SYS_PLD_CTRL2 register bit assignments.

Figure 3.16. SYS_PLD_CTL2 register

Table 3.10 lists the SYS_PLD_CTRL2 register bit assignments.

Table 3.10. SYS_PLD_CTRL2 register

Bits	Access	Name	Reset value	Description
[31:24]	Read as zero, write ignored.	-	`0x00`	Undefined.
[23:20]	Read Only	COMMRX	bxxxx	Comms channels receive.
[19:16]	Read Only	COMMTX	bxxxx	Comms channels transmit.
[15:12]	Read Only	STANDBYWFI	bxxxx	Individual WFI indicators. Indicates if an ARM11 MPCore CPU is in WFI state. See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360).
[11:8]	Read Only	SMPnAMP	bxxxx	Individual AMP or SMP mode indicators, one from each ARM11 MPCore CPU. 0: Indicates AMP mode (processor is not part of coherency) 1: Indicates SMP mode (processor is part of coherency) See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360).
[7:4]	Read Only	RESETREQ	bxxxx	Individual watchdog reset requests, one from each ARM11 MPCore CPU.
[3:0]	Read Only	PLDVER	bxxxx	PLD build version.

SYS_PLD_INIT

This register is located at SYSBASE+0x7C as follows:

Address [31:0]=0x1000007C

Note

This register is locked for write by SYS_LOCK. Write 0xA05F to 0x10000020 to unlock until next EB reset.

SYS_PLD_INIT values will only be updated after nPB reset.

Figure 3.17 shows the SYS_PLD_INIT register bit assignments.

Figure 3.17. SYS_PLD_INIT register

Table 3.11 lists the SYS_PLD_INIT register bit assignments.

Table 3.11. SYS_PLD_INIT register

Bits	Access	Name	Reset value	Description
[31:28]	Read/Write Lockable	PB divider	`b0000`	PB divider ratio that the PLL uses: 0000: pb-value is 1 0001: pb-value is 2 … 1111: pb-value is 16.
[27:24]	Read/Write Lockable	PA divider	`b0000`	PA divider ratio that the PLL uses: 0000: pa-value is 1 0001: pa-value is 2 … 1111: pa-value is 16.
[23:20]	Read/Write Lockable	N divider	`b1011`	N divider ratio that the PLL uses: 0000: n-value is 1 0001: n-value is 2 … 1111: n-value is 16.
[19]	Read/Write Lockable	M divider	`b0`	M divider ratio that the PLL uses: 0: m-value is 1 1: m-value is 2.
[18]	Read/Write Lockable	PBSTBY	`b0`	0: CLKB from PLL is active 1: CLKB from PLL is 0.
[17]	Read/Write Lockable	STBY	`b0`	0: CLKA from PLL is active 1: CLKA from PLL is 0.
[16]	Read/Write Lockable	PLLEN	`b1`	0: if committed and bit 0 of the PLL control test data register is 0 (its reset value) REFCLK will be selected as CLKOUT on the next rising edge of REFCLK 1: if committed, and bit 0 of the PLL control test data register is 0 (its reset value) the PLL will be selected as CLKOUT on the next rising edge of REFCLK. PLL enable is committed when STANDBYWFI[3:0] from the `mpcore_tc_module` == b1111 or the input signal CONFIGINIT == b1.
[15:4]	Read as zero, write ignored.	-	`0x000`	Undefined
[3:0]	Read/Write Lockable	CLKOUTDIV	`b0000`	The clock divider ratio to drive the AXI bus clock and the FPGA: 0000: CLKOUTDIV is equal to CLKIN 0001: CLKOUTDIV is CLKIN divided by 20010: CLKOUTDIV is CLKIN divided by 30011: CLKOUTDIV is CLKIN divided by 40100: CLKOUTDIV is CLKIN divided by 50101: CLKOUTDIV is CLKIN divided by 60110: CLKOUTDIV is CLKIN divided by 70111: CLKOUTDIV is CLKIN divided by 81000: CLKOUTDIV is CLKIN divided by 11001: CLKOUTDIV is CLKIN divided by 101010: CLKOUTDIV is CLKIN divided by 31011: CLKOUTDIV is CLKIN divided by 121100: CLKOUTDIV is CLKIN divided by 51101: CLKOUTDIV is CLKIN divided by 141110: CLKOUTDIV is CLKIN divided by 71111: CLKOUTDIV is CLKIN divided by 16

Changing the core to AXI bus clock ratio

The MPCore test chip PLL register value may be set by software to change the core to AXI bus clock ratio. The reference clock from the EB, REFCLK is a 20MHz clock. In Table 3.12, the PLL feedback divider and the test chip output divider values are always equal. For example, if the AXI bus runs at 20MHz and the core at 240MHz, this requires both dividers to divide by 12. The required SYS_PLD_INIT value is ratio option 12:1 in Table 3.12. The SYS_PLD_INIT register is described in EB system FPGA registers.

You can change the core to AXI clock frequency ratio to match a real system design as follows:

Write 0xA05F to 0x10000020 to unlock the SYS_PLD_INIT register.
Write the new value to the SYS_PLD_INIT register at 0x1000007C − example PLL values are given in Table 3.12.
Shut down the debugger and press the RESET push button on the EB to load the new setting.

Table 3.12. SYS_PLD_INT register values

Ratio option (core to bus)	SYS_PLD_INIT value
1:1	`0xFF010000`
2:1	`0x77110001`
3:1	`0x55210002`
4:1	`0x33310003`
5:1	`0x22410004`
6:1	`0x22510005`
7:1	`0x22610006`
8:1	`0x11710007`
10:1	`0x11910009`
12:1	`0x11B1000B`
14:1	`0x00D1000D`
16:1	`0x00F1000F`

SYS_VOLTAGE0

This register is located at SYSBASE+0xA0 as follows:

Address [31:0]=0x100000A0

Note

This register is locked for write by SYS_LOCK. Write 0xA05F to 0x10000020 to unlock until next EB reset.

Figure 3.18 shows the SYS_VOLTAGE0 register bit assignments.

Figure 3.18. SYS_VOLTAGE0 register

Table 3.13 lists the SYS_VOLTAGE0 register bit assignments.

Table 3.13. SYS_VOLTAGE0 register

Bits Access Name Reset value Description

[31:20]

Read as zero, write ignored.

Bits	Access	Name	Reset value	Description
[31:20]	Read as zero, write ignored.	-	`0x000`	Undefined
[19:8]	Read only	ADC_DATA	`0x000`	Reads the VDDCORE voltage for the MPCore. The LSB of the ADC reading corresponds to 610μV. The formula to calculate the supply voltage (`VDDCORE)` is: VDDCORE=INT(ADC_DATA[11:0](61010^-6))
[7:0]	Read/Write Lockable	DAC_DATA	`0x80`	Sets the VDDCORE voltage for the MPCore. The default value is 1.2V. Circuit values are typically chosen to give a ±0.25V adjustment range for the core voltage. A value of `0xFF` gives maximum negative offset from the default (-0.25V) and a value of `0x0` gives maximum positive offset from the default (+0.25V).

0x000

Undefined

[19:8]

Read only

ADC_DATA

0x000

Reads the VDDCORE voltage for the MPCore.

The LSB of the ADC reading corresponds to 610μV.

The formula to calculate the supply voltage (VDDCORE) is:

VDDCORE=INT(ADC_DATA[11:0]*(610*10^-6))

[7:0]

Read/Write Lockable

DAC_DATA

0x80

Sets the VDDCORE voltage for the MPCore. The default value is 1.2V.

Circuit values are typically chosen to give a ±0.25V adjustment range for the core voltage. A value of 0xFF gives maximum negative offset from the default (-0.25V) and a value of 0x0 gives maximum positive offset from the default (+0.25V).

SYS_VOLTAGE1

This register is located at SYSBASE+0xA4 as follows:

Address [31:0]=0x100000A4

Note

This register is locked for write by SYS_LOCK. Write 0xA05F to 0x10000020 to unlock until next EB reset.

Figure 3.19 shows the SYS_VOLTAGE1 register bit assignments.

Figure 3.19. SYS_VOLTAGE1 register

Table 3.14 lists the SYS_VOLTAGE1 register bit assignments.

Table 3.14. SYS_VOLTAGE1 register

Bits Access Name Reset value Description

[31:20]

Read as zero, write ignored.

Bits	Access	Name	Reset value	Description
[31:20]	Read as zero, write ignored.	-	`0x000`	Undefined
[19:8]	Read only	ADC_DATB	`0x000`	Reads the AVDD voltage for the ARM11 MPCore test chip PLL. The LSB of the ADC reading corresponds to 610μV. The formula to calculate the supply voltage (`AVDD)` is: AVDD=INT(ADC_DATB[11:0](61010^-6))
[7:0]	Read/Write Lockable	DAC_DATB	`0x80`	Sets the AVDD voltage for the ARM11 MPCore test chip PLL. The default value is 1.2V. Circuit values are typically chosen to give a ±0.25V adjustment range for the PLL voltage. A value of `0xFF` gives maximum negative offset from the default (-0.25V) and a value of `0x0` gives maximum positive offset from the default (+0.25V).

0x000

Undefined

[19:8]

Read only

ADC_DATB

0x000

Reads the AVDD voltage for the ARM11 MPCore test chip PLL.

The LSB of the ADC reading corresponds to 610μV.

The formula to calculate the supply voltage (AVDD) is:

AVDD=INT(ADC_DATB[11:0]*(610*10^-6))

[7:0]

Read/Write Lockable

DAC_DATB

0x80

Sets the AVDD voltage for the ARM11 MPCore test chip PLL. The default value is 1.2V.

Circuit values are typically chosen to give a ±0.25V adjustment range for the PLL voltage. A value of 0xFF gives maximum negative offset from the default (-0.25V) and a value of 0x0 gives maximum positive offset from the default (+0.25V).

SYS_VOLTAGE2

This register is located at SYSBASE+0xA8 as follows:

Address [31:0]=0x100000A8

Figure 3.20 shows the SYS_VOLTAGE2 register bit assignments.

Figure 3.20. SYS_VOLTAGE2 register

Table 3.15 lists the SYS_VOLTAGE2 register bit assignments.

Table 3.15. SYS_VOLTAGE2 register

Bits Access Name Reset value Description

[31:20]

Read as zero, write ignored.

Bits	Access	Name	Reset value	Description
[31:20]	Read as zero, write ignored.	-	`0x000`	Undefined
[19:8]	Read Only	ADC_DATC	`0x000`	Reads the VDDCORE current for the MPCore. To calculate the current (`IDDCORE`) use the formula: IDDCORE=INT(ADC_DATC[11:0](61010^-6))/R_SENSE*100 By default, the `R_SENSE` resistor is 0.025Ω.
[7:0]	Reserved	DAC_DATC	`0x00`	Legacy only (not used).

0x000

Undefined

[19:8]

Read Only

ADC_DATC

0x000

Reads the VDDCORE current for the MPCore.

To calculate the current (IDDCORE) use the formula:

IDDCORE=INT(ADC_DATC[11:0]*(610*10^-6))/R_SENSE*100

By default, the R_SENSE resistor is 0.025Ω.

[7:0]

Reserved

DAC_DATC

0x00

Legacy only (not used).

SYS_VOLTAGE3

This register is located at SYSBASE+0xAC as follows:

Address [31:0]=0x100000AC

Figure 3.21 shows the SYS_VOLTAGE3 register bit assignments.

Figure 3.21. SYS_VOLTAGE3 register

Table 3.16 lists the SYS_VOLTAGE3 register bit assignments.

Table 3.16. SYS_VOLTAGE3 register

Bits Access Name Reset value Description

[31:20]

Read as zero, write ignored.

Bits	Access	Name	Reset value	Description
[31:20]	Read as zero, write ignored.	-	`0x000`	Undefined
[19:8]	Read Only	ADC_DATD	`0x000`	Reads the AVDD current for the ARM11 MPCore test chip PLL. To calculate the current (`AIDD`) use the formula: AIDD=INT(ADC_DATD[11:0](61010^-6))/R_SENSE*100 By default, the `R_SENSE` resistor is 0.5Ω.
[7:0]	Reserved	DAC_DATD	`0x00`	Legacy only (not used).

0x000

Undefined

[19:8]

Read Only

ADC_DATD

0x000

Reads the AVDD current for the ARM11 MPCore test chip PLL.

To calculate the current (AIDD) use the formula:

AIDD=INT(ADC_DATD[11:0]*(610*10^-6))/R_SENSE*100

By default, the R_SENSE resistor is 0.5Ω.

[7:0]

Reserved

DAC_DATD

0x00

Legacy only (not used).

Copyright © 2005-2010 ARM Limited. All rights reserved.	ARM DUI 0318F
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