Core Tile for ARM11 MPCore User Guide: 3.8.1. CT11MPCore PLD signals

3.8.1. CT11MPCore PLD signals

The CT11MPCore PLD performs the following functions:

loading of data to the DACs that control the programmable power supplies (see Power supply control)
reading of data from the ADCs that monitor the ARM11 MPCore test chip voltages (see Reading the voltages and currents)
configuring the ARM11 MPCore test chip PLL on power up (see Clocks)
controlling the individual resets to the MPCore processors (see Resets)
controlling the interrupt mode that defines the interrupt routing (see Interrupts)
configuring the L2, AXI and memory sub-systems within the ARM11 MPCore test chip (see Chapter 4 Test Chip Hardware Description)
controlling the HDRZ signal multiplexers (see HDRZ signal mux).

Note

The binary image for the EB system FPGA depends on whether a tile is fitted in the remaining baseboard tile site. A further Core Tile or a Logic Tile may be fitted here for system prototyping. The application notes supplied include FPGA and PLD images for the current ARM supported tile combinations.

The CT11MPCore PLD is controlled by the serial interface signals listed in Table 3.4. These signals connect to the EB via the HDRZ header.

Table 3.4. PLD control signals

Signal	Description
PLDCLK	Clocks data into or out of the PLD
PLDD1	Serial data input to PLD
PLDD0	Serial data output from PLD
PLDnRESET	Resets the serial interface and signals the start of transfers

The EB system FPGA implements seven registers that hold values sent to and received from the CT11MPCore PLD using the 4-wire serial interface. The EB system FPGA provides the serialization and deserialization logic required for the interface. The interface timing is shown in Figure 3.14.

Figure 3.14. 4-wire serial interface timing

Data is output on the rising edge of PLDCLK and sampled on the falling edge. The interface is reset and re-synchronized by PLDnRESET after each 60 bit serial transfer. The rising edge of PLDnRESET also indicates the start of a transfer. The data is transferred MSB first in both directions across the interface.

Note

The PLDD0 serial data stream from the CT11MPCore PLD is only 43 bits long. Bits PLDD0[42:0] are used to transfer the data, PLDD0[59:43] are reserved and tied LOW.

The CT11MPCore PLD drives the configuration signals listed in Table 3.5.

Note

There are a total of 60 bits used in the Serial write data register serial data stream.

Table 3.5. Serial write data register

PLD Pin Name	Serial Bits PLDD1	Definition
RD_DIV[3:0]	3:0	ARM11 MPCore test chip PLL Clock divider. See Clock setting in reset mode.
RD_CTRL[31:16]	19:4	ARM11 MPCore test chip PLL Clock control. See Clock setting in reset mode.
PLLUPDATE	20	Start PLL update flag (reserved for future PLL support).
L2BYPASS	21	Selects the L2 cache bypassing: 0: you can use the L2 cache 1: the L2 cache is bypassed.
L2MASTNUM	22	Selects the number of L220 master ports: 0: one master port, M1. When one master is selected, master port 1 is used 1: two master ports, M0 and M1 are used. The port options available are shown in Figure 4.11. Note This bit is not currently user configurable and is set HIGH by the CT11MPCore PLD to select two L220 master ports when using the EB.
MPMASTNUM	23	Selects the number of ARM11 MPCore test chip master ports: 0: one master port, M0. When one master is selected, master port 0 is used 1: two master ports, M0 and M1 are used. The port options available are shown in Figure 4.11.
AXInOE0	24	AXI Mux output enable: 0: enable AXI Port 0 to Y headers 1: disable and isolate AXI Port 0 from Y headers. See AXI bus multiplexing.
HDRZEN	25	Header Z optional signal mux enable: 0: disable optional HDRZ signals 1: enable optional HDRZ signals. See HDRZ signal mux.
VINITHI[3:0]	29:26	When HIGH, indicates high-Vecs mode for the particular ARM11 MPCore processor.
CFGEND[1:0]	31:30	The U and EE bits reset values in the CP15 Control Register and E Bit reset value in CPSR/SPSR depend on the value of CFGEND[1:0]. See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360) for details.
nCPURESET[3:0]	35:32	Individual ARM11 MPCore processor resets.
DBGMUX[11:0]	47:36	Debug matrix select. Selects the external debug request and debug acknowledge routing between the four ARM11 MPCore CPUs to enable cross-triggering.
INTMODE[2:0]	50:48	Interrupt mode: bx00: Legacy bx01: New + DCC bx1x: New no DCC b1xx: FIQ[3:0] enable. See Interrupts.
DACDAT[7:0]	58:51	Voltage control, 8 bit DAC value applied to the DAC channel selected by DACSEL. See Setting the ARM11 MPCore test chip voltage.
DACSEL	59	Selects the voltage control DAC channel. See Setting the ARM11 MPCore test chip voltage.

The CT11MPCore PLD Serial read data register provides the status signals listed in Table 3.6.

Note

There are a total of 43 bits used in the Serial read data register data stream.

Table 3.6. Read serial data register

PLD Pin Name	Serial Bits PLDD0	Definition
PLOCK	0	ARM11 MPCore test chip PLL lock indicator. 0: ARM11 MPCore test chip PLL is not locked to REFCLK 1: ARM11 MPCore test chip PLL is locked to REFCLK. See Clock setting in reset mode.
ISP0nLOCK	1	ispClock5620 PLL lock indicator 0. 0: ispClock5620 PLL 0 is locked to CLKOUTDIVD 1: ispClock5620 PLL 0 is not locked to CLKOUTDIVD. See Clocks.
ISP1nLOCK	2	ispClock5620 PLL lock indicator 1. 0: ispClock5620 PLL 1 is locked to CLKOUTDIV 1: ispClock5620 PLL 1 is not locked to CLKOUTDIV. See Clocks.
PLLUPDATED	3	MPCore PLL settings status. 0: ARM11 MPCore test chip PLL settings are being updated. 1: ARM11 MPCore test chip PLL settings are complete.
RESETREQ[3:0]	7:4	Individual watchdog reset requests, one from each ARM11 MPCore CPU
SMPnAMP[3:0]	11:8	Individual AMP or SMP mode indicators, one from each MPCore CPU. 0: Indicates AMP mode (processor is not part of coherency) 1: Indicates SMP mode (processor is part of coherency) See the ARM11 MPCore Processor Technical Reference Manual (ARM DDI 0360).
STANDBYWFI[3:0]	15:12	Individual WFI indicators. Indicates if an MPCore CPU is in WFI state. See the ARM MPCore Processor Technical Reference Manual (ARM DDI 0360).
COMMTX[3:0]	19:16	Comms channel transmit from each ARM11 MPCore CPU.
COMMRX[3:0]	23:20	Comms channel receive from each ARM11 MPCore CPU.
ADCDAT[11:0]	35:24	Current sensing 12-bit ADC value (selected by ADCSEL[2:0]).
ADCSEL[2:0]	38:36	ADC channel currently being converted (ADCDAT value is from ADC channel ADCSEL - 1).
PLDVER[3:0]	42:39	PLD build version.
Reserved	59:43	Legacy only (not used).

Copyright © 2005-2010 ARM Limited. All rights reserved.	ARM DUI 0318F
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