Core Tile for ARM11 MPCore User GuideHBI-0146
Home > CT11MPCore Signal Descriptions > Links, test points, and LED indicators > Test points

5.2.2. Test points

Figure 5.4 shows the location of test points on the CT11MPCore. Table 5.6 lists the function of the signal at each test point.

Figure 5.4. Test point location


Table 5.6. Test point signal and description

Test pointSignalDescription
TP1REFOUT0Local clock generator CLK1 output.
TP2VDDCORE1V2 supply to the ARM11 MPCore test chip core.
TP3GNDGround (0V) reference loop for signal measurements.
TP4GNDGround (0V) reference loop for signal measurements.
TP7PLD_SPARE0Function not implemented, used in development only,
TP8nLOCK1Lock indicator. Indicates that the ISP1 clock generator is locked to CLKOUTDIV from test chip PLL.
TP9ISP1_9AISP1 clock generator output Bank 9A.
TP10ISP1_9BISP1 clock generator output Bank 9B.
TP11CLKOUTDIVInput clock to ISP1 clock generator from the test chip PLL.
TP12nLOCK0Lock indicator. Indicates that the ISP0 clock generator is locked to CLKOUTDIVD from the test chip PLL.
TP13ISP0_7AISP0 clock generator output Bank 7A.
TP14ISP0_7BISP0 clock generator output Bank 7B.
TP15CLKOUTDIVDInput clock to ISP0 clock generator from the test chip PLL.
TP16AVDD1V2 supply to the ARM11 MPCore test chip PLL.
TP171V81V8 supply to the PLD core.
TP18REFCLKReference clock from selected external source.
TP19RVALID0RVALID from AXI port 0.
TP20ARVALID0ARVALID from AXI port 0.
TP21RVALID1RVALID from AXI port 1.
TP22ARVALID1ARVALID from AXI port 1.

Note

TP5 and TP6 are not included on the production release of the Core Tile.

Copyright © 2005-2010 ARM Limited. All rights reserved.ARM DUI 0318F
PDF file icon  PDF version
Home > CT11MPCore Signal Descriptions > Links, test points, and LED indicators > Test points