Core Tile for ARM11MPCore™ User Guide


Table of Contents

About this book
Intended audience
Using this book
Typographical conventions
Further reading
Feedback on this document
Feedback on the ARM Core Tiles
1. Introduction
1.1. About the Core Tiles
1.2. Overview of CT11MPCore
1.2.1. System architecture
1.2.2. External logic
1.2.3. ARM processor test chip
1.2.4. PLD
1.2.5. Processor bus
1.2.6. Memory
1.2.7. Clock generation
1.2.8. JTAG
1.2.9. Power supply control
1.2.10. Links and indicators
1.3. Precautions
1.3.1. Ensuring safety
1.3.2. Preventing damage
2. Getting Started
2.1. Using the CT11MPCore with an Emulation Baseboard
2.2. Using the CT11MPCore with a custom baseboard
2.3. Connecting power
2.3.1. Supplying power to the EB
2.4. Connecting RealView ICE
2.4.1. Connecting a JTAG device to the EB
3. CT11MPCore Hardware Description
3.1. Core Tile architecture
3.2. About the ARM11 MPCore test chip
3.3. Clocks
3.3.1. Clock routing
3.3.2. Clock setting in reset mode
3.4. Resets and interrupts
3.4.1. Resets
3.4.2. Interrupts
3.5. HDRZ signal mux
3.6. Power supply control
3.6.1. Setting the ARM11 MPCore test chip voltage
3.6.2. Reading the voltages and currents
3.7. AXI bus multiplexing
3.7.1. Multiplexing scheme
3.8. Overview of Core Tile configuration
3.8.1. CT11MPCore PLD signals
3.8.2. Core configuration from ARM CP15
3.9. Memory configuration
3.10. Register configuration
3.10.1. ARM11 MPCore test chip registers
3.10.2. CT11MPCore serial registers
3.10.3. EB system FPGA registers
3.11. JTAG support
3.11.1. JTAG control and clock routing
3.11.2. JTAG debug mode scan chain routing
3.11.3. JTAG configuration mode scan chain routing
3.11.4. JTAG loopback control
3.11.5. Debug request and acknowledge routing
4. Test Chip Hardware Description
4.1. ARM11 MPCore test chip overview
4.2. Clocks
4.2.1. Clocking overview
4.2.2. PLL
4.2.3. PLL bypass module
4.2.4. Test chip PLL control register
4.2.5. Clock module
4.2.6. Test chip clock divider register
4.2.7. Clock signals overview
4.3. Resets and interrupts
4.3.1. Resets
4.3.2. Interrupts
4.4. Power supply control
4.5. Memory configuration
4.5.1. ARM11 MPCore
4.5.2. L220 cache controller
4.6. L220 bypass and peripheral decode
4.6.1. L220 bypass module
4.6.2. Peripheral decoder
4.7. Debug and JTAG configuration
4.7.1. TAP controller
4.7.2. Debug
4.7.3. JTAG Configuration
4.7.4. TAP ID registers
5. CT11MPCore Signal Descriptions
5.1. Header connectors
5.1.1. HDRX signals
5.1.2. HDRY signals
5.1.3. HDRZ signals
5.2. Links, test points, and LED indicators
5.2.1. Links
5.2.2. Test points
5.2.3. LED indicators
5.3. AXI bus timing specification
5.3.1. Core Tile timing and the AMBA 3 AXI Protocol
5.3.2. Timing parameters
A. Specifications
A.1. Electrical specification
A.1.1. Bus interface characteristics
A.1.2. Current requirements
A.2. Mechanical details

List of Figures

1.1. CT11MPCore layout
1.2. CT11MPCore and Emulation Baseboard
1.3. System block diagram
2.1. Core Tile, Logic Tile, and an Emulation Baseboard
2.2. EB power connectors
2.3. JTAG connection to an Emulation Baseboard
3.1. CT11MPCore block diagram
3.2. Clock routing and hardware initialization
3.3. RDATA1[31:0] data fields when using CONFIGINIT
3.4. Clock divider setting in reset mode, dividing by two
3.5. PLL setting in reset mode, multiplying by four
3.6. Reset routing
3.7. EB and CT11MPCore reset sequence
3.8. Interrupt mode signal routing
3.9. HDRZ signal mux
3.10. Voltage control and voltage and current monitoring
3.11. CT11MPCore AXI bus multiplexing scheme
3.12. CT11MPCore AXI mux timing
3.13. MPCore AXI multiplexing logic
3.14. 4-wire serial interface timing
3.15. SYS_PLD_CTRL1 register
3.16. SYS_PLD_CTL2 register
3.17. SYS_PLD_INIT register
3.18. SYS_VOLTAGE0 register
3.19. SYS_VOLTAGE1 register
3.20. SYS_VOLTAGE2 register
3.21. SYS_VOLTAGE3 register
3.22. JTAG debug mode routing (nCFGEN=1)
3.23. JTAG configuration mode routing (nCFGEN=0)
3.24. Additional JTAG configuration mode routing
3.25. JTAG debug (normal) mode scan chain routing (nCFGEN=1)
3.26. JTAG configuration mode scan chain (nCFGEN=0)
3.27. JTAG loopback control
4.1. Top-level view of ARM11 MPCore test chip
4.2. Clock domain overview
4.3. PLL block diagram
4.4. Test chip PLL control register
4.5. AXI bus clock
4.6. Test chip clock divider register
4.7. Test chip interrupt control register
4.8. Test chip power status register
4.9. L220 data RAM organization
4.10. L220 bypass mechanism
4.11. MPCore and L220 port configurations
4.12. Test chip and ARM11 MPCore TAP controller connections
4.13. TAP signal connections between the four ARM11 MPCore CPUs
4.14. TAP ID register
5.1. HDRX, HDRY, and HDRZ (upper) pin numbering
5.2. Location of links (bottom)
5.3. Location of links (top)
5.4. Test point location
5.5. LED indicator location
5.6. CT11MPCore multiplexed AXI bus input setup timing
5.7. CT11MPCore multiplexed AXI bus output valid timing
A.1. Board outline (top view)

Proprietary Notice

Words and logos marked with® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The Core Tile generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help


It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision AOctober 2005First release
Revision BDecember 2005Fixes for Errata
Revision CSeptember 2006Fixes for Errata
Revision DSeptember 2008Fixes for Errata
Revision EJanuary 2009Fixes for Errata
Revision FJuly 2010Document update
Copyright © 2005-2010 ARM Limited. All rights reserved.ARM DUI 0318F