This is an ARM family CPU that contains EmbeddedICE^® logic and Embedded Trace Macrocell™ (ETM). Figure 2.1 shows an example of how RealView Debugger can be joined with ARM ETM-enabled hardware to enable tracing capabilities.

The ETM monitors the ARM core buses, and passes compressed information through the trace port to the Trace Port Analyzer (TPA). To detect sequences of events performed by the processor, the on-chip ETM contains a number of resources that are selected when the ASIC is designed. These resources comprise the trigger and filter logic you utilize within RealView Debugger.

This is an ARM family CPU that contains EmbeddedICE logic, an Embedded Trace Buffer™ (ETB™), and an ETM. Figure 2.2 shows an example of how RealView Debugger can be joined with ARM ETB-enabled hardware to enable tracing capabilities.

The ETB stores data produced by the ETM. This is required for processors that run at higher speeds than can be supported by an external TPA. Therefore, trace information can be captured in real-time, and accessed by RealView Debugger at a reduced clock rate.

For details on how a processor with an ETB interacts with other trace hardware elements, see the documentation that accompanies the processor.

For ARM family CPUs that support the CoreSight architecture, trace capture is available from the CoreSight (CSETM). Figure 2.3 shows an example of how RealView Debugger can be joined with ARM hardware that supports CoreSight to enable tracing capabilities using the following CoreSight components:

For ARM family CPUs that support the CoreSight architecture, trace capture is available through the CoreSight ETB (CSETB). Figure 2.4 shows an example of how RealView Debugger can be joined with ARM hardware that supports CoreSight to enable tracing capabilities using the following CoreSight components:

This is a processor core based on the Intel XScale Microarchitecture core. The XScale core can only trace instructions, and does not trace data.