RealView Debugger Trace User GuideVersion 4.0
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2.2.1. ASIC that supports trace

You must have a target system that includes either an ARM® architecture-based ASIC or XScale™ processor.

ARM processor with an ETM

For ARM processors that contain EmbeddedICE® logic and Embedded Trace Macrocell™ (ETM™), you can capture trace directly from the ETM. Figure 2.1 shows an example of how RealView Debugger can be joined with ARM ETM-enabled hardware to enable tracing capabilities.

Figure 2.1. Trace hardware setup with ETM


The ETM monitors the ARM processor buses, and passes compressed information through the trace port to the Trace Port Analyzer (TPA). To detect sequences of events performed by the processor, the on-chip ETM contains a number of resources that are selected when the ASIC is designed. These resources comprise the trigger and filter logic you utilize within RealView Debugger.

Note

This is the default setup expected by RealView Debugger for development platforms that do not contain CoreSight™ components.

ARM processor with an ETM and ETB

For ARM processors that contain EmbeddedICE logic, an Embedded Trace Buffer™ (ETB™), and an ETM, you can view the trace captured by the ETB. Figure 2.2 shows an example of how RealView Debugger can be joined with ARM ETB-enabled hardware to enable tracing capabilities.

Figure 2.2. Trace hardware setup with ETB


The ETB stores data produced by the ETM. This is required for processors that run at higher speeds than can be supported by an external TPA. Therefore, trace information can be captured in real-time, and accessed by RealView Debugger at a reduced clock rate.

For details on how a processor with an ETB interacts with other trace hardware elements, see the documentation that accompanies the processor.

Note

Tracing an ASIC using an ETB does not require a TPA such as RealView Trace.

ARM processor that supports CoreSight ETM

For ARM processors that support the CoreSight architecture, trace capture is available from the CoreSight ETM (CSETM). Figure 2.3 shows an example of how RealView Debugger can be joined with ARM hardware that supports CoreSight to enable tracing capabilities using the following CoreSight components:

  • CSETM as the trace source

  • Trace Funnel (CSTFunnel), if the system has multiple trace sources

  • Trace Port Interface Unit (TPIU) as the trace sink with an off-chip trace port.

Figure 2.3. Trace hardware setup with CoreSight ETM


ARM processor with a CoreSight ETM and CoreSight ETB

For ARM processors that support the CoreSight architecture, trace capture is available through the CoreSight ETB (CSETB). Figure 2.4 shows an example of how RealView Debugger can be joined with ARM hardware that supports CoreSight to enable tracing capabilities using the following CoreSight components:

  • CSETM as the trace source (only one source can be selected at a time in this release)

  • CSETB as the trace sink

  • Trace Funnel (CSTFunnel), if the system has multiple trace sources.

Figure 2.4. Trace hardware setup with CoreSight ETB


XScale

This is a processor based on the Intel XScale Microarchitecture processor. The XScale processor can only trace instructions, and does not trace data.

See also

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