The PCAPT registers are listed in Table 4.2.
Table 4.2. Pin Capture registers
| Name | Address | Description |
|---|---|---|
| − | 0xCF200000 to 0xCF200054 | Reserved. Accesses within this address range will have unpredictable results. |
| ASYNCVIC | 0xCF200070 | Reads the value of the ASYNCVIC control signal and enables writing of a new value pending a system reset. See ASYNCVIC. |
| ClkCtl | 0xCF200080 | Controls Clock divider division values. See ClkCtl. |
| ClkEnCtl | 0xCF200084 | Controls Clock divider division values and clock sources. See ClkEnCtl. |
| IEMCtl | 0xCF200090 | Reads the SYNCMODEACK outputs and allows the SYNCMODEREQ inputs to the ARM1156T2F-S to be controlled. See IEMCtl. |
| TC-Control | 0xCF2000C0 | Controls a number of features of the ARM1156T2F-S test chip. See TC-Control. |
| BLKDISABL | 0xCF2000E0 | Controls the memory map decoders in the AXI bus matrix. Enables peripherals to be removed from the memory map and the released memory space to be redirected to the external AXI interface. See BLKDISABL. |
| ETMCtl | 0xCF20011C | Controls the source of ETMEXTINX to the ETM. See ETMCtl. |
| − | 0xCF200200 to 0xCF2FFFFF | Reserved. Accesses within this address range will have unpredictable results. |
The ASYNCVIC register allows setting and reading of ASYNCVIC that is used to drive the VIC interface signals IRQADDRVSYNCEN, INTSYNCEN and nVICSYNCEN. See ARM PrimeCell Vectored Interrupt Controller Technical Reference Manual (PL192) (DDI 0273) for details of the VIC port connections. By default, out of reset, this signal is driven HIGH to enable asynchronous interfaces. By writing to register bit [0] the state of the signal can be changed. Writes are held pending until the next system reset. Register bit [1] always reflects the actual state of ASYNCVIC and will only change after a system reset.
This register is located at PCAPTBASE+0x70 as
follows:
Address [31:0]=0xCF200070
Reset by: nPORESETX (power-on reset).
Figure 4.2 shows the ASYNCVIC register bit assignments.
Table 4.3 describes the ASYNCVIC register fields.
Table 4.3. ASYNCVIC register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:2] | Read as zero, write ignored. | - | 0x00000000 | Undefined. |
| [1] | Read only | ASYNCVIC | b1 | Reads the value of the ASYNCVIC control signal. |
| [0] | Read/Write | NewASYNCVIC | b1 | Write new value for the ASYNCVIC control signal, to be driven at next system reset. |
The ClkCtl, and ClkEnCtl clock registers control clock distribution in the ARM1156T2F-S test chip and are described in Clocks.
The IEMCtl register allows the IEM register slices SYNCMODEREQ inputs to be controlled and the SYNCMODEACK outputs to be read. There are also bits that allow pseudo-random strobing of SYNCMODEREQ. This can only be enabled when the corresponding SYNCMODEREQ control bit is set.
This register is located at PCAPTBASE+0x90 as
follows:
Address [31:0]=0xCF200090
Reset by: nPORESETX (power-on reset).
Figure 4.3 shows the IEMCtl register bit assignments.
Table 4.4 describes the IEMCtl register fields.
Table 4.4. IEMCtl register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:9] | Read as zero, write ignored. | - | 0x00000 | Undefined. |
| [8] | Read/Write | SYNCMODEREQP- random | b0 | When HIGH enables random strobing of the SYNCMODEREQ input to the P-port IEM register slice. At pseudo-random times SYNCMODEREQP is toggled and then waits for SYNCMODEACKP before toggling again. |
| [7] | Read/Write | SYNCMODEREQRW- random | b0 | When HIGH enables random strobing of the SYNCMODEREQ input to the RW-port IEM register slice. At pseudo-random times SYNCMODEREQRW is toggled and then waits for SYNCMODEACKRW before toggling again. |
| [6] | Read/Write | SYNCMODEREQI- random | b0 | When HIGH enables random strobing of the SYNCMODEREQ input to the I-port IEM register slice. At pseudo-random times SYNCMODEREQI is toggled and then waits for SYNCMODEACKI before toggling again. |
| [5] | Read only | SYNCMODEACKP | b0 | When HIGH indicates that the P-port IEM register slice has transitioned to synchronous mode. |
| [4] | Read only | SYNCMODEACKRW | b0 | When HIGH indicates that the RW-port IEM register slice has transitioned to synchronous mode. |
| [3] | Read only | SYNCMODEACKI | b0 | When HIGH indicates that the I-port IEM register slice has transitioned to synchronous mode. |
| [2] | Read/Write | SYNCMODEREQP | SYNCMODEREQD/P-init | IEM register slice control for the ARM1156T2F-S P-port. When HIGH the contents of the IEM register slice FIFO is multiplexed out of the AXI bus. |
| [1] | Read/Write | SYNCMODEREQRW | SYNCMODEREQI/RW-init | IEM register slice control for the ARM1156T2F-S RW-port. When HIGH the contents of the IEM register slice FIFO is multiplexed out of the AXI bus. |
| [0] | Read/Write | SYNCMODEREQI | SYNCMODEREQI/RW-init | IEM register slice control for the ARM1156T2F-S I-port. When HIGH the contents of the IEM register slice FIFO is multiplexed out of the AXI bus. |
Note
The Table 4.12 holds the programmable Reset values.
The TC-Control register controls a number of the features of the ARM1156T2F-S test chip.
This register is located at PCAPTBASE+0xC0 as
follows:
Address [31:0]=0xCF2000C0
Reset by: nPORESETX (power-on reset).
Figure 4.4 shows the TC-Control register bit assignments.
Table 4.5 describes the TC-Control register fields.
Table 4.5. TC-Control register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:4] | Read as zero, write ignored. | - | 0x0000000 | Undefined. |
| [3] | Read/Write | FIQISNMI | b0 | When HIGH enables Non-Maskable Fast Interrupt (nFIQ). |
| [2] | Read/Write | TEINIT | b0 | When HIGH indicates exceptions are taken in thumb. |
| [1] | Read/Write | ForceETMPWRUP | b0 | When HIGH forces ETMPWRUP (ETM powered up indicator) to the ARM1156T2F-S HIGH. |
| [0] | Read/Write | EnableVIC | b0 | When HIGH connects interrupt inputs nIRQ and nFIQ via the VIC. |
The BLKDISABL register controls the memory map decoders in the AXI bus matrix. By setting the appropriate register bit each of the peripherals can be removed from the memory map and the memory space automatically allocated to the external AXI interface. When all the register bits are set, all memory accesses are routed to the external AXI interface.
Caution
This register is implemented within the pin capture block. If the pin capture block is disabled, further writes to this register will not be possible and it will not be possible to re-enable the pin capture block.
This register is located at PCAPTBASE+0xE0 as
follows:
Address [31:0]=0xCF2000E0
Reset by: nPORESETX (power-on reset)
Figure 4.5 shows the BLKDISABL bit assignments.
Table 4.6 describes the BLKDISABL register fields.
Table 4.6. BLKDISABL register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:8] | Read as zero, write ignored. | - | 0x000000 | Undefined. |
| [7] | Read/Write | TCRAM | BLKDISABL-init[7] | Test chip RAM disable |
| [6] | Read/Write | ETM | BLKDISABL-init[6] | ETM disable |
| [5] | Read/Write | ETB | BLKDISABL-init[5] | ETB disable |
| [4] | Read/Write | PCAPT | BLKDISABL-init[4] | Pin Capture block disable |
| [3] | Read/Write | VIC | BLKDISABL-init[3] | VIC disable |
| [2] | Read/Write | RAM2 | BLKDISABL-init[2] | RAM2 memory disable |
| [1] | Read/Write | SPARE/DUMMY | BLKDISABL-init[1] | SPARE/DUMMY region disable |
| [0] | Read/Write | Unused | - | Declared for compatibility with AMBA logic |
Note
The Config-init register holds the programmable reset values.
The ETM Control Register selects the input sources for the CoreSight ETM11 EXTIN[3:0] bus.
This register is located at PCAPTBASE+0x11C as follows:
Address [31:0]=0xCF20011C
Reset by: nRESETX (system reset).
Figure 4.6 shows the ETM11CS bit assignments.
Table 4.7 describes the ETMCtl register fields.
Table 4.7. ETMCtl register bit assignments
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:6] | Read/Write | - | SBZ/UNP | Unused |
| [5:0] | Read/Write | EtmlnputSel | b000000 | Selects input sources for theETM11:
|
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