A simplified block diagram of the clock divider is shown in Figure 4.8.
Table 4.9 provides a description of the Clock divider signals.
Table 4.9. Clock divider signal description
| Name | Description | Function |
|---|---|---|
| PLLCLK | PLL clock | The PLL clock provides the reference frequency for the Clock divider. See PLL for details. |
| DIVCORE | CORECLK divisor | This is the CORECLK divider value. It is controlled by the DivCore field in the ClkCtl register. A default value is set in the DivCore-init field in the Config-init register by the CT1156T2F-S PLD during test chip initialization. |
| DIVInt | ACLK and ACLKENint divisor | This is the ACLK and ACLKENint divider value. It is controlled by the DivInt field in the ClkCtl register. A default divider value is set in the DivInt-init field in the Config-init register by the CT1156T2F-S PLD during test chip initialization. |
| DIVExt | ExtACLK and ExtACLKEn divisor | This is the ExtACLK and ExtACLKEn divider value. It is controlled by the DivExt field in the ClkCtl register. A default divider value is set in the DivExt-init field in the Config-init register by the CT1156T2F-S PLD during test chip initialization. |
| ACLKRatioRW | ACLKENRW divisor | This is the ACLKENRW divider value. It sets the CORECLK to ACLKENRW ratio. It is controlled by the ACLKRatioRW[3:0] field in the ClkEnCtl register. |
| ACLKSourceRW | ACLKENRW selector | When HIGH ACLKENRW is sourced from the ACLKENRW divider. When LOW ACLKENRW is sourced from the ACLKENint divider. It is controlled by the ACLKSourceRW bit in the ClkEnCtl register. |
| ACLKRatioI | ACLKENI divisor | This is the ACLKENI divider value. It sets the CORECLK to ACLKENI ratio. It is controlled by the ACLKRatioI field in the ClkEnCtl register. |
| ACLKSourceI | ACLKENI selector | When HIGH ACLKENI is sourced from the ACLKENI divider. When LOW ACLKENI is sourced from the ACLKENint divider. It is controlled by the ACLKSourceI bit in the ClkEnCtl register. |
| ACLKRatioP | ACLKENP divisor | This is the ACLKENP divider value. It sets the CORECLK to ACLKENP ratio. It is controlled by the ACLKRatioP field in the ClkEnCtl register. |
| ACLKSourceP | ACLKENP selector | When HIGH ACLKENP is sourced from the ACLKENP divider. When LOW ACLKENP is sourced from the ACLKENint divider. It is controlled by ACLKSourceP bit in the ClkEnCtl register. |
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