3.9.2. CT1156T2F-S serial registers
The CT1156T2F-S PLD implements two registers, the Serial
write data register and the Serial read data
register. These registers mirror the content of CT1156T2F-S specific registers
implemented in the baseboard system FPGA. The registers are continually updated
via a 4-wire serial link to ensure that the content of the CT1156T2F-S and baseboard
registers remains coherent.
The bit allocations for the Serial write data register are
shown in Table 3.4. The
bit allocations for the Serial read data register are
shown in Table 3.5.
Note
The Serial write data register and the Serial
read data register are only accessible via the 4-wire
serial link. Changing or reading the contents of these registers
is only possible by using Core Tile specific registers implemented
in the baseboard system FPGA. Not all fields in the Serial
write data register are user configurable, some are pre-configured
by the baseboard system FPGA.
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