The clock routing for the CT1156T2F-S and EB combination is shown in Figure 3.2. This figure also shows the clock hardware initialization signals.

Selection of the clock source for the Core Tile is controlled by CLKSEL from the CT1156T2F-S PLD. CLKSEL selects the clock source as CLK_NEG_DN_IN from the board above, or CLK_NEG_UP_IN from the board below. The value of CLKSEL is set locally during power up by the CT1156T2F-S PLD.

Figure 3.2. Clock routing and hardware initialization