This section describes the resets and contains the following subsections:
Several resets are required by the baseboard and the CT1156T2F-S test chip.
The reset logic on the baseboard initializes attached Logic Tiles and Core Tiles, the system FPGA, and external controllers as a result of a reset. The baseboard has several reset sources and generates several reset signals.
The EB reset sources and the function of the EB reset signals are described in the RealView Emulation Baseboard User Guide (ARM DUI0303).
The baseboard generates the nSYSPOR, nSYSRST, nWARMRST and nCOLDRST signals for the CT1156T2F-S.
The following signals are used to reset the ARM1156T2F-S test chip:
nPORESETX
nRESETX
The function of these signals is described in Chapter 4 Test Chip Hardware Description, in Resets.
The reset routing between the baseboard, CT1156T2F-S logic, and the ARM1156T2F-S test chip is shown in Figure 3.4 and comprises of:
- nSYSPOR
Power-on reset, active LOW.
- nSYSRST
System reset, active LOW.
- nCOLDRST
CT1156T2F-S specific software reset, active LOW.
- nWARMRST
CT1156T2F-S specific system reset, active LOW.
- PLLLOCKX
ARM1156T2F-S test chip PLL locked, active HIGH.
- ISP_nLOCK
ispClock5620 clock generator PLL locked, active LOW.
- GLOBAL_DONE
System FPGAs configured, active HIGH, open-collector.
- D_nSRST
Debug TAP controller reset. Active LOW, open-collector.
Correct initialization of a Core Tile and its associated baseboard requires a timed reset sequence. Details of the EB reset sequence are detailed in the RealView Emulation Baseboard User Guide (ARM DUI 0303). The power-on reset timing required when using a CT1156T2F-S in combination with a baseboard is shown in Figure 3.5. The reset signals are described in Table 3.1.
Table 3.1 describes the reset signals. A reset controller, implemented in the baseboard system FPGA, monitors the reset sources and generates the appropriate reset signals.
Table 3.1. Reset signals
| Name | Function |
|---|---|
| nBOARDPOR | This signal resets the baseboard system FPGA. This signal is also used to generate D_nTRST at power on. |
| D_nTRST | Open-collector debug TAP controller reset (the baseboard drives this signal with nBOARDPOR.) |
| GLOBAL_DONE | A configuration signal, active during reset. This is an open-collector configuration signal that goes HIGH when all FPGAs have finished configuring. The system is held in reset until this signal goes HIGH. |
| nSYSPOR | Power-on reset signal that initializes the reset level state machine in the baseboard system FPGA. There is a fixed 7μs delay after GLOBAL_DONE goes HIGH before nSYSPOR is released. Functions also as the power-on reset signal for the ARM1156T2F-S test chip logic. |
| nCOLDRST | A Core Tile specific software reset signal generated from nSYSPOR by the baseboard system FPGA. |
| ISP_nLOCK | An ispClock5620 clock generator status signal. ISP_nLOCK indicates when the clock generator is locked to ACLKX. It is used with PLLLOCKX to control the PLLLOCK bit that is used by the baseboard reset controller to determine when all clocks are stable and the main system reset, nSYSRST and the CT1156T2F-S specific reset, nWARMRST can be released. |
| PLLLOCKX | A PLL status signal. PLLLOCKX indicates when the ARM1156T2F-S test chip PLL is locked to REFCLK. It is used with ISP_nLOCK to control the PLLLOCK bit that is used by the baseboard reset controller to determine when all clocks are stable and the main system reset, nSYSRST and the CT1156T2F-S specific reset, nWARMRST can be released. |
| PLLLOCK | A CT1156T2F-S status signal sent to the baseboard via the 4-wire serial interface. PLLLOCK goes HIGH when PLLLOCKX and ISP_nLOCK indicate that all CT1156T2F-S derived clocks are stable. |
| nSYSRST | Main system reset. |
| nWARMRST | A Core Tile specific system reset signal generated from nSYSRST by the baseboard system FPGA. |
| nPORESETX | ARM1156T2F-S test chip logic power-on reset. |
| nRESETX | ARM1156T2F-S test chip reset. |
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