Core Tile for ARM1156T2F-S User Guide: 3.7. Overview of Core Tile configuration

3.7. Overview of Core Tile configuration

The ARM1156T2F-S test chip, clock source, voltage levels, and a number of system parameters are configurable on the CT1156T2F-S. In a final product, core configuration is static and the core configuration signals are tied HIGH or LOW and the voltage and clocks are fixed. However, the CT1156T2F-S allows you to program these signals for experimentation.

There are several ways that CT1156T2F-S configuration occurs:

The CT1156T2F-S PLD.
This is the primary configuration source. The PLD serial registers are described in CT1156T2F-S serial registers.
Note
The extent of configuration performed by the CT1156T2F-S PLD is dependant on the type of reset applied to the Core Tile.
CT1156T2F-S specific configuration registers in the baseboard system FPGA. These registers allow you to change several of the parameters controlled by the CT1156T2F-S PLD.
See Application Note AN158 (ARM DAI 0158) supplied on the Versatile CD for details of the registers implemented in the EB system FPGA.
Signals present on the Core Tile connector HDRZ.
Control registers in the ARM1156T2F-S test chip.
The control registers in the test chip are described in Chapter 4 Test Chip Hardware Description.
Control registers in the ARM1156T2F-S.
For details of the registers in the ARM1156T2F-S see the ARM1156T2F-S Technical Reference Manual (ARM DDI 0290)

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3.7. Overview of Core Tile configuration

Note