The Pin Capture block (PCAPT) within the ARM1156T2F-S test chip contains the ClkCtl and ClkEnCtl registers that control the ARM1156T2F-S test chip clocks.
Caution
There are a number of restrictions to the way that clock generation can be controlled by the clock control registers. It is strongly advised that you use the default clock configuration settings applied by the CT1156T2F-S PLD during power-on reset.
The Pin Capture block base address, PCAPTBASE, is 0xCF20,0000.
The clock control register definitions are:
This register is located at PCAPTBASE+0x80 as
follows:
Address [31:0]=0xCF200080
Reset by: nPORESETX (power-on reset)
Figure 4.9 shows the ClkCtl register bit assignments.
Table 4.10 lists the ClkCtl register fields.
Table 4.10. ClkCtl register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:22] | Read as zero, write ignored. | - | b0 | Undefined. |
| [21] | Read/Write | AMBAClkSource | AMBAClkSource-init | not used |
| [20] | Read as zero, write ignored. | - | b0 | Undefined. |
| [19:14] | Read/Write | DivExt | DivExt-init[5:0] | Sets the PLLCLK to ExtACLK and ExtACLKEn divider value in the test chip Clock divider. See Clock divider. |
| [13] | Read as zero, write ignored. | - | b0 | Undefined. |
| [12:7] | Read/Write | DivInt | DivInt-init[5:0] | Sets the PLLCLK to ACLK and ACLKENint divider value in the test chip Clock divider. See Clock divider. |
| [6] | Read as zero, write ignored. | - | b0 | Undefined. |
| [5:0] | Read/Write | DivCore | DivCore-init[5:0] | Sets the PLLCLK to CORECLK divider value in the test chip Clock divider. See Clock divider. |
Note
The Config-init register holds the programmable reset values.
This register is located at PCAPTBASE+0x84 as
follows:
Address [31:0]=0xCF200084
Reset by: nPORESETX (power-on reset).
Figure 4.10 shows the ClkEnCtl register bit assignments.
Table 4.11 lists the ClkEnCtl register fields.
Table 4.11. ClkEnCtl register
| Bits | Access | Name | Reset value | Description |
|---|---|---|---|---|
| [31:20] | Read as zero, write ignored. | - | 0x000 | Undefined. |
| [19] | Read/Write | ACLKSourceP | AMBAClkSource-init | When HIGH: Sources ACLKENP from the ACLKRatioP divider. When LOW: Sources ACLKENP from the ACLKENint divider. See Clock divider. |
| [18] | Read as zero, write ignored. | ACLKSourceD | b0 | Not used in ARM1156T2F-S test chip |
| [17] | Read/Write | ACLKSourceRW | AMBAClkSource-init | When HIGH: Sources ACLKENRW from the ACLKRatioRW divider. When LOW: Sources ACLKENRW from the ACLKENint divider. See Clock divider. |
| [16] | Read/Write | ACLKSourceI | AMBAClkSource-init | When HIGH: Sources ACLKENI from the ACLKRatioI divider. When LOW: Sources ACLKENI from the ACLKENint divider. See Clock divider. |
| [15:12] | Read/Write | ACLKRatioP | 0x0 | Sets the CORECLK to ACLKENP ratio. |
| [11:8] | Read as zero, write ignored. | - | 0x0 | Undefined. |
| [7:4] | Read/Write | ACLKRatioRW | 0x0 | Sets the CORECLK to ACLKENRW ratio. |
| [3:0] | Read/Write | ACLKRatioI | 0x0 | Sets the CORECLK to ACLKENI ratio. |
Note
The Config-init register holds the programmable reset values.
PDF version