Core Tiles are development boards that enable you to develop products based on ARM^® processors and AMBA^® interfaces. Core Tiles are built around test chips, which are ASIC implementations of one or more ARM processors. Core Tiles provide one or more AMBA interfaces from the processor so that it can be connected to an AMBA-based system. See the AMBA Specification (ARM IHI 0011) and the AMBA 3 AXI Protocol Specification (ARM IHI 0022) for further information.

The Core Tile must be used in conjunction with a specific baseboard that implements the necessary system and memory controllers in an FPGA. For example, the CT1156T2F-S when combined with the RealView^® Emulation Baseboard (EB) will provide a standalone system for product development. Third-party or custom development systems may also be used with a Core Tile.

Core Tiles do not have power or JTAG connectors. The tiles must be stacked on a baseboard that provides power and JTAG connections. The Core Tiles also require a reference clock (or clocks) to be supplied by the attached baseboard.

Through-board connectors on tile products allow stacking of multiple tiles. Multiple combinations of Core Tile and Logic Tile can be used to create a multiprocessor system.

For debug, a Realview Analyzer Tile can be used to provide access to signals on the tile header connectors.