Core Tile for ARM1156T2F-S User Guide: 3.10. JTAG support

3.10. JTAG support

JTAG signals are present on both the upper and lower HDRZ connectors. An external board provides the JTAG connector and the routing of the JTAG signals from the connector to HDRZ (see JTAG control and clock routing). The Core Tile routes the JTAG scan path through devices on the board. The logic devices that are placed in the Core Tile scan chain depend on the JTAG mode:

Debug mode: Debug mode is the default mode used for general system development and debug. In this mode, the JTAG signals flow through the Debug Scan Chain (this scan chain connects to the ARM1156T2F-S test chip only). The JTAG signals used for debug are identified by the D_ prefix.
Note
Common access to the ARM1156T2F-S DBGTAP controllers is available in this mode. See Debug.
Configuration mode: In configuration mode the PLD, clock generator, and the ARM1156T2F-S test chip are placed into the scan chain. This mode allows the programmable logic devices in the system to be reprogrammed and the ARM1156T2F-S test chip registers to be configured.
To select configuration mode, the baseboard pulls the nCFGEN signal LOW on the Core Tile. This reroutes the JTAG scan path. The JTAG signals used for configuration are identified by the C_ prefix.
Note
Access to the ARM1156T2F-S test chip boundary scan TAP controller is available in this mode. See JTAG Configuration.

Table 3.6 provides a description of the JTAG signals.

Note

In the description in Table 3.6, the term JTAG equipment refers to any hardware that can drive the JTAG signals to devices in the scan-chain. Typically, RealView ICE is used, although you can also use hardware from third-party suppliers to debug ARM processors.

Table 3.6. JTAG signal description

Name	Description	Function
nBSTAPEN	Boundary scan TAP enable	In configuration mode, the boundary scan TAP logic in a test chip is enabled. Note nBSTAPEN drives the nBSTAPENX control pin on the ARM1156T2F-S test chip. In JTAG configuration mode, nBSTAPEN is LOW and the ARM1156T2F-S test chip TAP controller is enabled. In JTAG debug mode, nBSTAPEN is HIGH and the DBGTAP controller in the ARM1156T2F-S is enabled.
EDGREQ	Debug request (from JTAG equipment)	EDGREQ is a request to the ARM1156T2F-S to enter the debug state.
DBGACK	Debug acknowledge (to JTAG equipment)	DBGACK indicates to the debugger that the ARM1156T2F-S has entered debug state.
nCFGEN	Configuration enable (controlled by config slide-switch on the EB)	nCFGEN is an active LOW signal used to put all boards in the tile stack into configuration mode. In configuration mode all FPGAs and PLDs are connected to the scan chain so that they can be configured by the JTAG equipment.
nRTCKEN	Return TCK enable (from Core Tile to EB)	nRTCKEN is an active LOW signal driven by any Core Tile that requires RTCK to be routed back to the JTAG equipment. If nRTCKEN is HIGH, the baseboard drives RTCK LOW. If nRTCKEN is LOW, the baseboard drives the TCK signal back up the stack to the JTAG equipment.
nTRST, D_nTRST, C_nTRST	Test reset (from JTAG equipment)	This active LOW open-collector signal is used to reset the JTAG port and the associated debug circuitry on the processor. It is asserted at power-up by each module, and can be driven by the JTAG equipment. D_nTRST is the reset for the debug mode scan chain and C_nTRST is the reset for the configuration mode scan chain. Note D_nTRST is always tied to D_nSRST. C_nTRST is tied to D_nTRST when configuration mode is enabled.
RTCK, D_RTCK	Return TCK (to JTAG equipment)	Some devices sample TCK (for example a synthesizable core with only one clock), and this has the effect of delaying the time when a component actually captures data. RTCK is a mechanism for returning the sampled clock to the JTAG equipment, so that the clock is not advanced until the synchronizing device has captured the data. In a multiple device JTAG chain, the D_RTCK output from a component connects to the TCK input of the down-stream device. The RTCK signal on the EB connector HDRZ returns TCK to the JTAG equipment. D_RTCK is the RTCK signal in the debug scan chain. RTCK is not available in the configuration mode scan chain.
TCK, D_TCK, C_TCK	Test clock (from JTAG equipment)	TCK synchronizes all JTAG transactions. TCK connects to all JTAG components in the scan chain. Series termination resistors are used to reduce reflections and maintain good signal integrity. TCK flows up the stack of modules and connects to each JTAG component. However, if there is a device in the scan chain that synchronizes TCK to some other clock, then all down-stream devices are connected to the RTCK signal on that component (see RTCK). D_TCK is the clock for the debug mode scan chain and C_TCK is the clock for the configuration mode scan chain.
TDI, D_TDI, C_TDI	Test data in (from JTAG equipment)	TDI goes up the stack of tiles from the baseboard (or Interface Module) and then back down the stack (as TDO) connecting to each component in the scan chain. D_TDI is the data signal for the debug mode scan chain and C_TDI is the data signal for the configuration mode scan chain.
TDO, D_TDO, C_TDO	Test data out (to JTAG equipment)	TDO is the return path of the data input signal TDI. For a stack of RealView products, TDI goes up to the top of the stack and returns down as TDO. The JTAG components are connected in the return path so that the length of track driven by the last component in the chain is kept as short as possible. D_TDO is the data signal for the debug mode scan chain and C_TDO is the data signal for the configuration mode scan chain.
TMS, D_TMS, C_TMS	Test mode select (from JTAG equipment)	TMS controls transitions in the tap controller state machine. TMS connects to all JTAG components in the scan chain. D_TMS is the control signal for the debug mode scan chain and C_TMS is the control signal for the configuration mode scan chain.

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