Core Tile for ARM1156T2F-S User Guide

HBI-0154


Table of Contents

Preface
About this book
Intended audience
Using this book
Typographical conventions
Other conventions
Further reading
Feedback
Feedback on this document
Feedback on the ARM Core Tiles
1. Introduction
1.1. About Core Tiles
1.2. Overview of CT1156T2F-S
1.2.1. System architecture
1.2.2. External logic
1.2.3. ARM processor test chip
1.2.4. PLD
1.2.5. Processor bus
1.2.6. Memory
1.2.7. Clock generation
1.2.8. JTAG
1.2.9. Power supply control
1.2.10. Indicators
1.3. Precautions
1.3.1. Ensuring safety
1.3.2. Preventing damage
2. Getting Started
2.1. Using the CT1156T2F-S with an Emulation Baseboard
2.2. Using the CT1156T2F-S with a custom baseboard
2.3. Connecting power
2.3.1. Supplying power to the EB
2.4. Connecting JTAG debugging equipment
2.4.1. Connecting a JTAG device to the EB
2.5. Connecting Trace
2.5.1. Connecting the Trace Port Analyzer
3. CT1156T2F-S Hardware Description
3.1. Core Tile architecture
3.2. About the ARM1156T2F-S test chip
3.3. Clocks
3.3.1. Clock routing
3.3.2. Clock setting in reset mode
3.4. Resets and interrupts
3.4.1. Resets
3.4.2. Interrupts
3.5. Power supply control
3.5.1. Setting the CT1156T2F-S test chip voltage
3.5.2. Reading the voltages and currents
3.6. AXI bus multiplexing
3.6.1. Multiplexing scheme
3.7. Overview of Core Tile configuration
3.7.1. CT1156T2F-S PLD
3.7.2. ARM1156T2F-S test chip configuration
3.7.3. Core configuration from ARM CP15
3.8. Memory configuration
3.9. Register configuration
3.9.1. ARM1156T2F-S test chip registers
3.9.2. CT1156T2F-S serial registers
3.9.3. Baseboard system FPGA registers
3.10. JTAG support
3.10.1. JTAG control and clock routing
3.10.2. JTAG debug mode scan chain routing
3.10.3. JTAG configuration mode scan chain routing
3.10.4. JTAG loopback control
3.11. Trace support
4. Test Chip Hardware Description
4.1. ARM1156T2F-S test chip overview
4.1.1. Block descriptions
4.2. Memory map
4.3. Pin capture block
4.3.1. Register Definitions
4.4. Clocks
4.4.1. Clocking overview
4.4.2. PLL
4.4.3. Clock divider
4.4.4. Clock control registers
4.5. Test chip configuration
4.5.1. Config-init register
4.6. Resets and interrupts
4.6.1. Resets
4.6.2. Interrupts
4.7. Debug and JTAG configuration
4.7.1. TAP controller
4.7.2. Debug
4.7.3. JTAG Configuration
4.7.4. TAP ID registers
5. CT1156T2F-S Signal Descriptions
5.1. Header connectors
5.1.1. HDRX signals
5.1.2. HDRY signals
5.1.3. HDRZ signals
5.2. Trace Connectors
5.2.1. Trace connector pinout
5.3. Links, test points, and LED indicators
5.3.1. Links
5.3.2. Test points
5.3.3. LED indicators
5.4. AXI bus timing specification
5.4.1. Core Tile timing and the AMBA 3 AXI Protocol
5.4.2. Timing parameters
A. Specifications
A.1. Electrical specification
A.1.1. Bus interface characteristics
A.1.2. Current requirements
A.2. Mechanical details
Glossary

List of Figures

1. Key to timing diagram conventions
1.1. CT1156T2F-S layout
1.2. CT1156T2F-S and Emulation Baseboard
1.3. System block diagram
2.1. Core Tile, Logic Tile, and an Emulation Baseboard
2.2. EB power connectors
2.3. JTAG connection to an Emulation Baseboard
2.4. Trace connection with RealView Trace
3.1. CT1156T2F-S block diagram
3.2. Clock routing and hardware initialization
3.3. Power-on ARM1156T2F-S test chip configuration timing
3.4. Reset routing
3.5. Baseboard and CT1156T2F-S power-on reset sequence
3.6. Voltage control and voltage and current monitoring
3.7. CT1156T2F-S AXI bus multiplexing scheme
3.8. CT1156T2F-S AXI mux timing
3.9. ARM1156T2F-S AXI multiplexing logic
3.10. 4-wire serial interface timing
3.11. Configuration timing − power-on reset
3.12. Configuration timing − full software reset
3.13. Configuration timing − system reset
3.14. JTAG debug mode routing (nCFGEN=1)
3.15. JTAG configuration mode routing (nCFGEN=0)
3.16. Additional JTAG configuration mode routing
3.17. JTAG debug (normal) mode scan chain routing (nCFGEN=1)
3.18. JTAG configuration mode scan chain (nCFGEN=0)
3.19. JTAG loopback control
4.1. Top-level view of ARM1156T2F-S test chip
4.2. ASYNCVIC register bit assignments
4.3. IEMCtl register bit assignments
4.4. TC-Control register bit assignments
4.5. BLKDISABL register bit assignments
4.6. ETMCtl register bit assignments
4.7. PLL block diagram
4.8. Clock divider block diagram
4.9. ClkCtl bit assignments
4.10. ClkEnCtl bit assignments
4.11. Config-init bit assignments
4.12. Test chip and ARM1156T2F-S TAP controller connections
4.13. TAP ID register
5.1. HDRX, HDRY, and HDRZ (upper) pin numbering
5.2. AMP Mictor connector
5.3. Location of links (top)
5.4. Location of links (bottom)
5.5. Test point location
5.6. LED indicator location
5.7. CT1156T2F-S multiplexed AXI bus input setup timing
5.8. CT1156T2F-S multiplexed AXI bus output valid timing
A.1. Board outline (top view)

Proprietary Notice

Words and logos marked with® or ™ are registered trademarks or trademarks of ARM Limited in the EU and other countries, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Neither the whole nor any part of the information contained in, or the product described in, this document may be adapted or reproduced in any material form except with the prior written permission of the copyright holder.

The product described in this document is subject to continuous developments and improvements. All particulars of the product and its use contained in this document are given by ARM Limited in good faith. However, all warranties implied or expressed, including but not limited to implied warranties of merchantability, or fitness for purpose, are excluded.

This document is intended only to assist the reader in the use of the product. ARM Limited shall not be liable for any loss or damage arising from the use of any information in this document, or any error or omission in such information, or any incorrect use of the product.

Confidentiality Status

This document is Non-Confidential. The right to use, copy and disclose this document may be subject to license restrictions in accordance with the terms of the agreement entered into by ARM and the party that ARM delivered this document to.

Product Status

The information in this document is final, that is for a developed product.

Conformance Notices

This section contains conformance notices.

Federal Communications Commission Notice

This device is test equipment and consequently is exempt from part 15 of the FCC Rules under section 15.103 (c).

CE Declaration of Conformity

The system should be powered down when not in use.

The Core Tile generates, uses, and can radiate radio frequency energy and may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment causes harmful interference to radio or television reception, which can be determined by turning the equipment off or on, you are encouraged to try to correct the interference by one or more of the following measures:

  • ensure attached cables do not lie across the card

  • reorient the receiving antenna

  • increase the distance between the equipment and the receiver

  • connect the equipment into an outlet on a circuit different from that to which the receiver is connected

  • consult the dealer or an experienced radio/TV technician for help

Note

It is recommended that wherever possible shielded interface cables be used.

Revision History
Revision AOctober 2006First release
Revision BOctober 2007Second release updated to fix documentation defects
Revision CApril 2011Third release updated to fix a documentation defect.
Copyright © 2006-2011 ARM Limited. All rights reserved.ARM DUI 0331C