A.1. Header connectors

Figure A.1 shows the pin numbers and power-blade usage of the HDRX, HDRY, and HDRZ headers on the upper side of the tile.

Figure A.1. HDRX, HDRY, and HDRZ (upper) pin numbering

Note

The FPGA I/O bank connections to the VCCO1 and VCCO2 power blades are shown in Table 3.6.

The Foldover logic can reroute some of the signals normally on the upper header connectors back to the lower connectors and some of the signals normally on the lower header connectors back to the upper connectors. See Foldover for details.

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