3.3.1. PLD serial interface

Serial control of the configuration PLD is achieved through a three wire interface. Two additional control signals, LOCAL_DONE and SDL are also required to ensure the PLD logic is in a defined state before the data stream is loaded. A simplified diagram of the serial interface and the clock distribution is shown in Figure 3.9.

Figure 3.9. PLD serial interface

The interface timing in Debug mode is shown in Figure 3.10. All data bits are clocked OUT on the rising edge of CLK_24MHZ and IN on the falling edge of CLK_24MHZ. At the end of each data stream SDL is asserted to load the last data stream and signal the start of a new data stream. The SDI and SDO data streams are of equal length (74 bits) but only bits SDI[19:0] carry data, the remaining 54 bits SDI[73:20] are set to zero. Data is transferred MSB first by both streams. The serial streams are constantly running to ensure both FPGA and PLD registers are identical in content.

Figure 3.10. PLD serial interface timing

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