3.3.2. PLD serial data

The serial interface between the FPGA and the PLD is used to reduce the pin count for slow interfaces. In Debug mode it provides a bidirectional link between the FPGA and the PLD, effectively increasing the pin count of the FPGA.

Table 3.14 lists the contents of the FPGA to PLD serial data stream (SDO).

Table 3.14. FPGA to PLD serial data stream

BitFPGA to PLD (SDO)Description
[73:71]OSC2_S[2:0]Clock source 2 output divider value.
[70:62]OSC2_V[8:0]Clock source 2 VCO divider value.
[61:55]OSC2_R[6:0]Clock source 2 reference divider value.
[54:52]OSC1_S[2:0]Clock source 1 output divider value.
[51:43]OSC1_V[8:0]Clock source 1 VCO divider value.
[42:36]OSC1_R[6:0]Clock source 1 reference divider value.
[35:33]OSC0_S[2:0]Clock source 0 output divider value.
[32:24]OSC0_V[8:0]Clock source 0 VCO divider value.
[23:17]OSC0_R[6:0]Clock source 0 reference divider value.
[16:15]ReservedFor future expansion.
[14]GLBCLKENSet HIGH if CLK_GLOBAL is to be sourced by the LT-XC4VLX100+.
[13]RTCKENSet HIGH if nRTCKEN is to be sourced by the LT-XC4VLX100+.
[12]ZTHRUHDRZ Thru switch control: Set HIGH to activate HDRZ Thru switches.
[11]ZLFOLDHDRZ Lower Foldover switch control: Set HIGH to activate HDRZ Lower Foldover switches.
[10]ZUFOLDHDRZ Upper Foldover switch control: Set HIGH to activate HDRZ Upper Foldover switches.
[9]YTHRUHDRY Thru switch control: Set HIGH to activate HDRY Thru switches.
[8]YLFOLDHDRY Lower Foldover switch control: Set HIGH to activate HDRY Lower Foldover switches.
[7]YUFOLDHDRY Upper Foldover switch control: Set HIGH to activate HDRY Upper Foldover switches.
[6]XTHRUHDRX through switch control: Set HIGH to activate HDRX Thru switches.
[5]XLFOLDHDRX Lower Foldover switch control: Set HIGH to activate HDRX Lower Foldover switches.
[4]XUFOLDHDRX Upper Foldover switch control: Set HIGH to activate HDRX Upper Foldover switches.
[3]LED[7]User[7] LED control, user defined. Set HIGH to switch LED ON.
[2]LED[6]User[6] LED control, user defined. Set HIGH to switch LED ON.
[1]LED[5]User[5] LED control, user defined. Set HIGH to switch LED ON.
[0]LED[4]User[4] LED control, user defined. Set HIGH to switch LED ON.

Table 3.15 lists the contents of the PLD to FPGA serial data stream (SDI).

Table 3.15. PLD to FPGA serial data stream

BitPLD to FPGA (SDI) 
[73:20]Set to zeroNot used.
[19]PLDVER[7]Firmware build version number bit[7]
[18]PLDVER[6]Firmware build version number bit[6]
[17]PLDVER[5]Firmware build version number bit[5]
[16]PLDVER[4]Firmware build version number bit[4]
[15]PLDVER[3]Firmware build version number bit[3]
[14]PLDVER[2]Firmware build version number bit[2]
[13]PLDVER[1]Firmware build version number bit[1]
[12]PLDVER[0]Firmware build version number bit[0]
[11]PCBREV[2]PCB revision number bit[2]
[10]PCBREV[1]PCB revision number bit[1]
[9]PCBREV[0]PCB revision number bit[0]
[8]nPBPush-button status: LOW when general purpose push-button is pressed.
[7]SW[7]User switch S1[8] status: HIGH when switch is ON.
[6]SW[6]User switch S1[7] status: HIGH when switch is ON.
[5]SW[5]User switch S1[6] status: HIGH when switch is ON.
[4]SW[4]User switch S1[5] status: HIGH when switch is ON.
[3]SW[3]User switch S1[4] status: HIGH when switch is ON.
[2]SW[2]User switch S1[3] status: HIGH when switch is ON.
[1]SW[1]User switch S1[2] status: HIGH when switch is ON.
[0]SW[0]User switch S1[1] status: HIGH when switch is ON.

Caution

Do not load the PLD with any image other than that supplied on the CD that accompanies the tile, or an updated version downloaded from the ARM web site at www.arm.com/support/downloads/. Loading an incorrect image might render the board unusable. If the image in the PLD has been accidently erased, you can reload the image into the PLD by setting the CONFIG slide-switch (or inserting the CONFIG link) on the baseboard and using the Progcards utility to reprogram the PLD.

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