| |||
Home > Hardware Description > Test points |
The test points listed in Table 3.18 enable you to measure clock frequencies and supply voltages, and to monitor the control port between the PLD and the FPGA. The location of the test points on the LT-XC4VLX100+ is shown in Figure 3.27.
Table 3.18. Test points
Test Point | Signal | Description |
---|---|---|
TP1 | DOUT_BUSY | Virtex-4 configuration signal (not used). |
TP2 | CLK_GLOBAL_IN | Buffered version of global clock signal. This is fed to a GCLK input of the FPGA. |
TP3 | CLK_GLOBAL_OUT | Buffered version of global clock signal from the FPGA. (This signal is driven even if CLK_GLOBAL_OUT is disabled.) |
TP4 | CLK_OUT | Buffered version of clock signal CLK_OUT_TO_BUF that drives the buffers for the dual/differential clocking scheme:
|
TP5 | REF2_OUT | Buffered version of the fixed-frequency 24MHZ reference clock that feeds CLK_24MHZ_FPGA and CLK_24MHZ_PLD. |
TP6 | CLK_SCLK | Buffered version of the serial data input clock to the programmable oscillators. |
TP7 | 2V5 | I/O AUX voltage supply for the Virtex-4 FPGA (generated locally from 5V). Also supplies the tile temperature monitoring analog circuitry. |
TP8 | 1V8 | Core supply for the configuration PLD (generated locally from 5V). |
TP9 | 1V2 | Core supply for the Virtex-4 FPGA (generated locally from 5V). |
TP10 - TP13 | GND | Ground reference points. |
TP14 - TP21 | CFG_D[0] - CFG_D[7] | Serial link between the control PLD and the Virtex-4 FPGA. Link function is dependant on the PLD operating mode. See PLD. |
TP22 | PLD_SPARE0 | General purpose testpoint (pin 9 on PLD). Signal being monitored is determined by PLD image. |
TP23 | PLD_SPARE1 | General purpose testpoint (pin 10 on PLD). Signal being monitored is determined by PLD image. |