3.8. Test points

The test points listed in Table 3.18 enable you to measure clock frequencies and supply voltages, and to monitor the control port between the PLD and the FPGA. The location of the test points on the LT-XC4VLX100+ is shown in Figure 3.27.

Table 3.18. Test points

Test PointSignalDescription
TP1DOUT_BUSYVirtex-4 configuration signal (not used).
TP2CLK_GLOBAL_INBuffered version of global clock signal. This is fed to a GCLK input of the FPGA.
TP3CLK_GLOBAL_OUTBuffered version of global clock signal from the FPGA. (This signal is driven even if CLK_GLOBAL_OUT is disabled.)
TP4CLK_OUT

Buffered version of clock signal CLK_OUT_TO_BUF that drives the buffers for the dual/differential clocking scheme:

  • CLK_OUT_PLUS1

  • CLK_OUT_PLUS2

  • CLK_OUT_MINUS1

  • CLK_OUT_MINUS2

  • CLK_BUF_LOOP.

TP5REF2_OUTBuffered version of the fixed-frequency 24MHZ reference clock that feeds CLK_24MHZ_FPGA and CLK_24MHZ_PLD.
TP6CLK_SCLKBuffered version of the serial data input clock to the programmable oscillators.
TP72V5I/O AUX voltage supply for the Virtex-4 FPGA (generated locally from 5V). Also supplies the tile temperature monitoring analog circuitry.
TP81V8Core supply for the configuration PLD (generated locally from 5V).
TP91V2Core supply for the Virtex-4 FPGA (generated locally from 5V).
TP10 - TP13GNDGround reference points.
TP14 - TP21CFG_D[0] - CFG_D[7]Serial link between the control PLD and the Virtex-4 FPGA. Link function is dependant on the PLD operating mode. See PLD.
TP22PLD_SPARE0General purpose testpoint (pin 9 on PLD). Signal being monitored is determined by PLD image.
TP23PLD_SPARE1General purpose testpoint (pin 10 on PLD). Signal being monitored is determined by PLD image.

Figure 3.27. Testpoint locations

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