3.4.4. Delay-matched clock distribution (2 up / 2 down)

The Logic Tile enables a signal to be distributed to up to five tiles without requiring use of the DLLs to phase realign the signal. (The trace paths are organized such that all source-destination lengths are equal.) The tile generates five versions of a reference clock. These signals are routed to the two tiles above and the two tiles below.

Each tile can also receive four clocks (from the two tiles above and the two tiles below) as shown in Figure 3.20.

One board in a system can provide a master clock for a five-board system, consisting of the board generating the signal and two boards above and below it. The path lengths for the clock signals are matched so that all clocks are in phase. (The delay loop on the generating tile is equal to the path delays in the signals reaching the other four tiles. The other tiles do not retime the signal, but rely on the path lengths.) See Figure 3.20.

Figure 3.19. Delay-matched clocking scheme

Figure 3.20. Delay-matched clocks for five tiles

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