RealView® LT-XC4VLX100+ User Guide: 3.2.1. Variable I/O levels

3.2.1. Variable I/O levels

All HDRZ and HDRY connector signals are fixed at a 3.3V I/O signalling level.

The XU and XL I/O signalling levels are set to 3.3V by 0Ω links on the tile. You can however, remove the links and allow the VCCO blade of a corresponding connector on a plugged-in board to set the signal level. The signal levels for the FPGA banks are listed in Table 3.6. (All ARM Logic Tiles operate at a 3.3 V I/O signal level, but custom tiles may use a different signal level and supply the voltage to the VCCO blade.)

Table 3.6. FPGA I/O bank signal level

IO bank	Signal Level	Source
Bank 0 - 2, Bank 5 - 7, Bank 9 - 11, Bank 13, Bank 15	3V3	See Figure A.1 for 3V3 power blade positions.
Bank 4, Bank 8, Bank 16	VCCO1	HDRX upper header power blade (P0-P3). Tied to 3V3 if 0Ω link R49 is fitted. Remove R49 to supply VCCO from the tile above.
Bank 3, Bank 12, Bank 14	VCCO2	HDRX lower header power blade (P0-P3). Tied to 3V3 if 0Ω link R50 is fitted. Remove R50 to supply VCCO from the tile below.

Caution

If you provide VCCO from an adjacent tile, you must remove the relevant 0Ω resistor.

If you require any configuration resistor to be removed or changed, it is recommended that the work be carried out by a skilled technician with experience in circuit board soldering. If any board malfunction is proved as a result of any modification to the board or components, this immediately invalidates the warranty and could lead to costs from ARM for repair or replacement.

All pins on the lower HDRX connector must operate at 3.3V signal levels if the tile is used with an EB, PB926EJ-S, IM-LT1 or IM-LT3.

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