### 3.4.1. Onboard programmable clock generators

Three programmable clocks are supplied to the FPGA I/O pins by three serially programmable ICS307M-02 clock sources, as shown in Figure 3.12. These are general purpose clock sources and can be used for your design.

Figure 3.12. Programmable clock generators

#### Reference clocks

The first oscillator in the chain (OSC0) also provides the fixed-frequency 24MHz clocks CLK_24MHZ_FPGA and CLK_24MHZ_PLD.

#### ICS307M-02 clock generation functional overview

The ICS307M-02 clock sources are supplied with a reference clock by a 24MHz crystal oscillator. The frequency of the outputs from the ICS307M-02 clock sources are controlled by values loaded at the serial data pins. This enables them to produce a wide range of frequencies. Refer to the manufacturer’s web site, `www.icst.com `for more information.

#### Programming the clocks

The frequency of the clock from an ICS307M-02 is set by loading values for the divider and multiplier registers into the serial input port on the clock generator. These control the value of the parameters used to determine the output of the ICS307M-02.

### Note

CLK1 and CLK2 in the text below refers to the signals on the ICS307-01/02 data sheet, not to CLK1 and CLK2 on the Logic Tile. CLK1 outputs from the ICS307M-02 provide the system clocks and the CLK2 outputs are set to output the 24MHz reference frequency.

You can calculate the frequency of CLK1 using the formula:

where:

VDW

Is the VCO divider word: 4 – 511 (0, 1, 2, 3 are not permitted).

RDW

Is the reference divider word: 1 – 127 (0 is not permitted).

### Caution

For a 24MHz reference source the following constraints apply:

and

This requires the value of RDW to be within the range 1 − 117.

OD

Is the divide ratio: 2 - 10 (selected by S[2:0]).

See Table 3.16 for the available OD (Output Divider) settings.

Table 3.16. ICS307M-02 OD settings

S2S1S0DIVIDE
00010
0012
0108
0114
1005
1017
1103
1116

The full configuration data stream (CLK_DATA) from the PLD is shown in Figure 3.13 where:

C[1:0]

Internal load capacitance for crystal. If an external clock is used, C[1:0] is set to `b00`. See the ICS307-01/02 data sheet for details of capacitance values.

T

Duty cycle threshold setting:

The PLD sets the duty-cycle reference point to VDD/2. T is set to `b1`.

F[1:0]

Function of second output:

The PLD selects the reference signal as source. F is set to `b00`.

S[2:0]

Output divider select (OD).

V[8:0]

VCO divider word (VDW).

R[6:0]

Reference divider word (RDW).

Figure 3.13. VCO configuration data

### Note

CLK_DATA is loaded MSB first into the ICS307M-02 shift register. Data is clocked into the register on the rising edge of SCLK. The STROBE signal is pulsed HIGH after all bits have been shifted into the register.

Serial control of the programmable clocks is implemented in the PLD design. The C[1:0], T, and F[1:0] fields are fixed and are hard-coded in the PLD design. The S[2:0], V[8:0] and R[6:0] fields are system dependant and are set in Debug mode by the FPGA serial interface to the PLD. See Table 3.14 and `ltxc4vlx100_gtl.v` supplied on the Versatile CD for example values.

For information on the ICS clock generator see the ICS web site at `www.icst.com`.