RealView® LT-XC4VLX100+ User GuideLogic Tile HBI-0158
Home > Hardware Description > PLD

3.3. PLD

The Virtex-4 series of FPGAs has less general purpose I/O available than the Virtex-II series fitted on the LT-XC2V4000+ Logic Tile. To maintain the same level of user I/O at the X/Y/Z headers (918 pins maximum) several of the non timing critical signals associated with switches and LED indicators on the LT-XC4VLX100+ are first connected to the PLD. The status of these signals is then passed between the PLD and the Virtex-4 FPGA using a duplex serial link.

The configuration PLD has three modes of operation:

Configuration mode − Flash Programming

The Flash memory address, data, and control signals are passed serially to the PLD from the FPGA using CFG_D[7:0]. The PLD de-serializes the Flash signals and directly controls the Flash programming. A simplified diagram is shown in Figure 3.6.

Note

Use the Progcards utility to program the Flash using the JTAG port on the baseboard. If provided, the USB debug port on the baseboard can also be used to program the Flash. This utility first loads a Flash programmer image into the FPGA, then writes the bit file to the Flash memory. You can also use this utility to verify the Flash image against the bit file. See Downloading new FPGA configurations into Flash for details.

Figure 3.6. Flash memory programming

Debug mode − FPGA configuration from Flash memory

On power up, the FPGA is configured using the CFG_D[7:0] inputs. The PLD acts as an address counter incrementing the Flash memory address until FPGA configuration is complete. A simplified diagram is shown in Figure 3.7.

Figure 3.7. FPGA configuration from Flash

Debug mode − Normal operation

After FPGA configuration, the PLD switches the CFG_D[7:0] inputs to the FPGA over to normal Logic Tile functions. A simplified diagram is shown in Figure 3.8.

Figure 3.8. Normal operation

The operating mode is determined by the values of CFGEN and LOCAL_DONE.

CFGEN

This is a buffered and inverted version of nCFGEN, the global configuration signal.

LOCAL_DONE

This indicates that this tile configuration is complete.

The functions of the CFG_D[7:0] pins on the FPGA depend on the mode selected. Table 3.13 lists the pin function for each of the three PLD operating modes.

Table 3.13. CFG_D[7:0] pin functions

FPGA PinConfiguration mode: Flash programming CFGEN=1 LOCAL_DONE=XDebug mode: FPGA configuration CFGEN=0 LOCAL_DONE=0Debug mode: Normal operation CFGEN=0 LOCAL_DONE=1

CFG_D0

Flash programmingFD7 (config Flash data 0)SDL (serial data load)

CFG_D1

Flash programmingFD6 (config Flash data 1)SDO (serial data out)

CFG_D2

Flash programmingFD5 (config Flash data 2)SDI (serial data in)

CFG_D3

Flash programmingFD4 (config Flash data 3)ALWAYS_ONE

CFG_D4

Flash programmingFD3 (config Flash data 4)USER_LED[0]

CFG_D5

Flash programmingFD2 (config Flash data 5)USER_LED[1]

CFG_D6

Flash programmingFD1 (config Flash data 6)USER_LED[2]

CFG_D7

Flash programmingFD0 (config Flash data 7)USER_LED[3]
Copyright © 2006-2008 ARM Limited. All rights reserved.ARM DUI 0345D
Non-Confidential
PDF file icon  PDF version
Home > Hardware Description > PLD