3.4.2. Global clock

Tiles can receive the global clock or transmit the global clock to all of the boards in the tile stack. Figure 3.14 shows how global clock source selection is controlled.

The CLK_GLOBAL signal is present on all Logic Tiles. The signal, after buffering, goes to the CLK_GLOBAL_IN input of the FPGAs.

The FPGA on each tile outputs a CLK_GLOBAL_OUT signal to a tristate buffer. When the LT-XC4VLX100+ is the global clock source, the signal, CLK_GLBL_nEN from the PLD enables the buffer and the local signal, CLK_GLOBAL_OUT becomes the global clock, CLK_GLOBAL for the system.


The buffers are placed close to the HDRZ connectors, but there will be some skew between tiles. To use in-phase clock signals, use the CLK_NEG_x, CLK_POS_x, CLK_IN_x, or CLK_OUT_x signals.

Figure 3.14. Global clock source selection

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