3.4.3. Retimed clocks on multiple tiles

A number of the FPGA GCLK inputs and I/O pins enable the FPGA to generate or accept two clocks from the tile above or below as shown in Figure 3.15. (These can be differential clocks.)

Figure 3.15. Retimed clocking scheme

A differential clock (or two single-ended clocks) can be distributed upwards or downwards to any number of Logic Tiles in the stack. Each tile can use DLLs (in the Virtex-4 FPGA) to phase-align the clock outputs to the source clock. The PCB track lengths for the CLK_LOOPx signal traces are the same length as the total length of the output and input traces and the connector height. The local clock signals sent along the CLK_LOOPx are inputs to the DLLs and the delay time is used to retime the clocks. The CLK_LOOPx signals are not associated with particular clocks. The retiming is such that the clock edge used in the tile FPGA occurs at the same time as the clock edge on the adjacent tile. Figure 3.16 shows the DLL connection. Examples of how to route the synchronized clocks between multiple tiles are shown in Figure 3.17 (routing is shown from the bottom tile) and Figure 3.18 (routing is shown from the middle tile).

Figure 3.16. Clock retiming using a DLL


There are upper and lower frequency limitations in the retimed clock scheme because of the frequency limits for the DLLs.

There are limitations in the Virtex-4 clock routing that result in CLK_NEG_DN and CLK_NEG_UP being mapped to local BUFG resources when using single-ended clocks.

Figure 3.17. Retimed clock routing for three tiles (from bottom tile)

Figure 3.18. Retimed clock routing for three tiles (from middle tile)

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