3.2.2. Foldover

Because the tile headers have more I/O pins than the FPGA can support, some header pins are not normally connected to the FPGA, however, switches are provided to:

Foldover provides more I/O from the tile to support future platforms. See Figure 3.3 for a simplified block diagram of the Foldover logic and Table 3.7 through to Table 3.12 for a detailed list of the Foldover and Thru connections.

Figure 3.3. Simplified view of Foldover and Thru signals

The Foldover switches are controlled by outputs from the PLD. The FPGA uses CFG_D1 (SDO, serial data out from the FPGA in Debug mode) to serially output switch configuration information to the PLD. The serial interface reduces the number of FPGA I/O pins required for static configuration of the Logic Tile. Your FPGA design must instantiate the HDL that implements the serial Foldover control. An example implementation is provided on the CD that accompanies the tile.

Figure 3.4 shows an example of using the Foldover switches to increase the available connections between the FPGAs in a two tile stack. Pins YU[35:0} on the top LT-XC4VLX100+ are unused by the stack and the FPGA pins that connect to them are re-routed back down the stack for access by the lower Logic Tile using the Upper Foldover and Lower Foldover switches and the spare HDRY header pins Y[179:144].

Figure 3.4. Two tile Foldover example

Figure 3.5 shows an example of using the Foldover switches to increase the available connections between the top and bottom Logic Tile in a three tile stack. Pins YU[35:0} on the top LT-XC4VLX100+ are unused by the stack and so the FPGA pins that connect to them are re-routed back down the stack for access by the bottom Logic Tile using the Upper Foldover, Thru, and Lower Foldover switches and the spare HDRY header pins Y[179:144].

Figure 3.5. Three tile Foldover example

The Upper Foldover connections for HDRX are shown in Table 3.7.

Table 3.7. HDRX Upper Foldover connection

Lower headerFoldover (nXU_FOLD LOW)Thru (nX_THRU LOW)
XL178XU0XU178
XL179XU1XU179
XL176XU2XU176
XL177XU3XU177
XL174XU4XU174
XL175XU5XU175
XL172XU6XU172
XL173XU7XU173
XL170XU8XU170
XL171XU9XU171
XL168XU10XU168
XL169XU11XU169
XL166XU12XU166
XL167XU13XU167
XL164XU14XU164
XL165XU15XU165
XL162XU16XU162
XL163XU17XU163
XL160XU18XU160
XL161XU19XU161
XL158XU20XU158
XL159XU21XU159
XL156XU22XU156
XL157XU23XU157
XL154XU24XU154
XL155XU25XU155
XL152XU26XU152
XL153XU27XU153
XL150XU28XU150
XL151XU29XU151
XL148XU30XU148
XL149XU31XU149
XL146XU32XU146
XL147XU33XU147
XL144XU34XU144
XL145XU35XU145

The Lower Foldover connections for HDRX are shown in Table 3.8

Table 3.8. HDRX Lower Foldover connection

Upper headerFoldover (nXL_FOLD LOW)Thru (nX_THRU LOW)
XU178XL0XL178
XU179XL1XL179
XU176XL2XL176
XU177XL3XL177
XU174XL4XL174
XU175XL5XL175
XU172XL6XL172
XU173XL7XL173
XU170XL8XL170
XU171XL9XL171
XU168XL10XL168
XU169XL11XL169
XU166XL12XL166
XU167XL13XL167
XU164XL14XL164
XU165XL15XL165
XU162XL16XL162
XU163XL17XL163
XU160XL18XL160
XU161XL19XL161
XU158XL20XL158
XU159XL21XL159
XU156XL22XL156
XU157XL23XL157
XU154XL24XL154
XU155XL25XL155
XU152XL26XL152
XU153XL27XL153
XU150XL28XL150
XU151XL29XL151
XU148XL30XL148
XU149XL31XL149
XU146XL32XL146
XU147XL33XL147
XU144XL34XL144
XU145XL35XL145

The Upper Foldover connections for HDRY are shown in Table 3.9.

Table 3.9. HDRY Upper Foldover connection

Lower headerFoldover (nYU_FOLD LOW)Thru (nY_THRU LOW)
YL178YU0YU178
YL179YU1YU179
YL176YU2YU176
YL177YU3YU177
YL174YU4YU174
YL175YU5YU175
YL172YU6YU172
YL173YU7YU173
YL170YU8YU170
YL171YU9YU171
YL168YU10YU168
YL169YU11YU169
YL166YU12YU166
YL167YU13YU167
YL164YU14YU164
YL165YU15YU165
YL162YU16YU162
YL163YU17YU163
YL160YU18YU160
YL161YU19YU161
YL158YU20YU158
YL159YU21YU159
YL156YU22YU156
YL157YU23YU157
YL154YU24YU154
YL155YU25YU155
YL152YU26YU152
YL153YU27YU153
YL150YU28YU150
YL151YU29YU151
YL148YU30YU148
YL149YU31YU149
YL146YU32YU146
YL147YU33YU147
YL144YU34YU144
YL145YU35YU145

The Lower Foldover connections for HDRY are shown in Table 3.10.

Table 3.10. HDRY Lower Foldover connection

Upper headerFoldover (nYL_FOLD LOW)Thru (nY_THRU LOW)
YU178YL0YL178
YU179YL1YL179
YU176YL2YL176
YU177YL3YL177
YU174YL4YL174
YU175YL5YL175
YU172YL6YL172
YU173YL7YL173
YU170YL8YL170
YU171YL9YL171
YU168YL10YL168
YU169YL11YL169
YU166YL12YL166
YU167YL13YL167
YU164YL14YL164
YU165YL15YL165
YU162YL16YL162
YU163YL17YL163
YU160YL18YL160
YU161YL19YL161
YU158YL20YL158
YU159YL21YL159
YU156YL22YL156
YU157YL23YL157
YU154YL24YL154
YU155YL25YL155
YU152YL26YL152
YU153YL27YL153
YU150YL28YL150
YU151YL29YL151
YU148YL30YL148
YU149YL31YL149
YU146YL32YL146
YU147YL33YL147
YU144YL34YL144
YU145YL35YL145

The Upper Foldover connections for HDRZ are shown in Table 3.11.

Table 3.11. HDRZ Upper Foldover connection

Lower headerFoldover (nZU_FOLD LOW)Thru (nZ_THRU LOW)
ZL254ZU128ZU254
ZL255ZU129ZU255
ZL252ZU130ZU252
ZL253ZU131ZU253
ZL250ZU132ZU250
ZL251ZU133ZU251
ZL248ZU134ZU248
ZL249ZU135ZU249
ZL246ZU136ZU246
ZL247ZU137ZU247
ZL244ZU138ZU244
ZL245ZU139ZU245
ZL242ZU140ZU242
ZL243ZU141ZU243
ZL240ZU142ZU240
ZL241ZU143ZU241
ZL238ZU144ZU238
ZL239ZU145ZU239
ZL236ZU146ZU236
ZL237ZU147ZU237
ZL234[1]--
ZL235ZU149ZU235

[1] This pin is not controlled by the nZU_FOLD and nZ_THRU signals

The Lower Foldover connections for HDRZ are shown in Table 3.12.

Table 3.12. HDRZ Lower Foldover connection

Upper headerFoldover (nZL_FOLD LOW)Thru (nZ_THRU LOW)
ZU254ZL128ZL254
ZU255ZL129ZL255
ZU252ZL130ZL252
ZU253ZL131ZL253
ZU250ZL132ZL250
ZU251ZL133ZL251
ZU248ZL134ZL248
ZU249ZL135ZL249
ZU246ZL136ZL246
ZU247ZL137ZL247
ZU244ZL138ZL244
ZU245ZL139ZL245
ZU242ZL140ZL242
ZU243ZL141ZL243
ZU240ZL142ZL240
ZU241ZL143ZL241
ZU238ZL144ZL238
ZU239ZL145ZL239
ZU236ZL146ZL236
ZU237ZL147ZL237
ZU234[1]--
ZU235ZL149ZL235

[1] This pin is not controlled by the nZL_FOLD and nZ_THRU signals.

Note

The numbering for the matched pins for HDRX, HDRY, and HDRZ (for example, ZL238 – ZU144 and ZL239 – ZU145, ZL236 – ZU146 and ZL237 – ZU147) is to keep the polarity of differential signal pairs in the correct order on the header connector. If differential signaling is used, even-numbered pins are negative logic and odd-numbered pins are positive logic.

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