1.1. About the LT-XC4VLX100+ Logic Tile

The LT-XC4VLX100+ Logic Tile is designed as a platform for developing systems based on Advanced Microcontroller Bus Architecture (AMBA™) that use the Advanced eXtensible Interface (AXI), Advanced High-performance Bus (AHB), Advanced Peripheral Bus (APB) peripherals, or custom logic for use with ARM cores.

Note

The Logic Tile must be used with an external board that provides power and JTAG connectors. For standalone operation an Integrator® Interface Module (IM-LT1 or IM-LT3) is required. The Logic Tile can be used with a baseboard to provide additional development resources. Examples are the RealView Emulation Baseboard (EB) or the RealView Platform Baseboard for ARM926EJ-S (PB926EJ-S).

Some examples of how the Logic Tile can be used are:

Figure 1.1 shows the layout of the Logic Tile.

The LT-XC4VLX100+ can be supplied fitted with different Xilinx FPGAs:

XC4VLX160

Contains a Xilinx XC4VLX160-10 FPGA.

XC4VLX200

Contains a Xilinx XC4VLX200-10 FPGA.

The functionality of the Logic Tile is defined by a configuration image loaded into the FPGA at power-up. Application Notes are available that describe how to implement both AHB and AXI peripherals in Logic Tiles. Refer to the documentation supplied with the product on the Versatile CD and the Application Notes listing at www.arm.com/documentation for further details.

You can also download your own configurations to Flash using the JTAG connector or the USB debug port if this is provided on the baseboard. It is also possible to load an image directly to the FPGA but directly loaded images are lost when power is removed (see Reconfiguring the FPGA directly).

Table 1.1 compares the main features of the Virtex-II and Virtex-4 Logic Tiles.

Table 1.1. Comparison of Virtex-II and Virtex-4 Logic Tiles

FeatureLT-XC2V6/8000LT-XC4VLX160/200Notes
FPGA slices34K / 47K68K / 89KApproximately 50% bigger and up to 40% faster.
Header X/Y/Z I/O pins914 / 918918Equivalent to LT-XC2V8000 Logic Tile.
External clocks2621CLK_LOOP3 and CLK_LOOP4 removed as not normally used.
Tile clocks44OSC_CLK[2:0] and CLK_24MHz.
ZBT SRAM4MB

Can use FPGA block RAM:

  • up to 0.6MB on LX160

  • up to 0.7MB on LX200.

Config Flash images22 
User LEDs, switches48 
User push button11 
Config / Normal JTAGYesYes 
Header X/Y/Z FoldoverUpperUpper, LowerLower foldover added to increase available I/O in the tile stacks.
Variable I/O voltageHDRX, HDRYHDRX 
Resets22 
Over temperature indicatorNoYesRed LED indicator at board edge
Bit file encryptionTriple DES256b AESVirtex-4 key is not programmed in production

Figure 1.1. LT-XC4VLX100+ layout

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