1.2. Logic Tile architecture

Figure 1.2 shows the architecture of the Logic Tile.

Figure 1.2. System architecture

The Logic Tile comprises the following:

These components are discussed in detail in Chapter 3 Hardware Description.

Note

The Virtex-4 series of FPGAs has less general purpose I/O available than the Virtex-II series used on the LT-XC2V4000+ Logic Tile. To maintain the same level of user I/O at the X/Y/Z headers (918 pins maximum) several of the non timing critical signals associated with switches and LED indicators on the LT-XC4VLX100+ are first connected to the PLD. The status of these signals is then passed between the PLD and the Virtex-4 FPGA using a duplex serial link. See PLD for details.

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