3.5. Reset control

The LT-XC4VLX100+ has several reset signals. The reset architecture when used with an Emulation Baseboard for example, is shown in Figure 3.21, the full EB reset architecture has been cut down for clarity. See the RealView Emulation Baseboard User Guide (DUI 0303) for full details of the EB reset architecture if required.

As configuration of the Logic Tile is linked to the reset process Figure 3.21 also shows the control of FPGA_nPROG by the JTAG and Power-On-Reset (POR) circuits. Figure 3.22 shows the power-on reset sequence, and Table 3.17 describes the global reset signals.

Figure 3.21. Reset and configuration control

Figure 3.22. Power-on reset sequence

Note

The release of GLOBAL_DONE depends on other boards in the system having completed configuration.

Table 3.17. Reset signal descriptions

Name

Description

Function

nPOR

Tile Power-on reset

This signal is the LT-XC4VLX100+ Power-On-Reset. It is also used to generate the FPGA_nPROG pulse at power on.

nSRST

System reset

nSRST is an active LOW open-collector signal that can be driven by the JTAG equipment to reset the target board. Some JTAG equipment senses this line to determine when you have reset a board.

When the signal is driven LOW by the reset controller on the tile, the motherboard resets the whole system by driving nSYSRST LOW.

This is also used in Configuration mode as the initialization signal (FPGA_nINIT) to the FPGA.

Though not a JTAG signal, nSRST is described because it can be controlled by JTAG equipment.

Note

nSRST splits into two signals, D_nSRST and C_nSRST, to provide the debug and configuration signals on HDRZ.

nSYSRST

System reset

A system-wide, master reset signal from the baseboard (for example the EB). This signal is typically used to reset ARM cores, peripherals and user logic. Can be activated from several sources, including GLOBAL_DONE=0. (See the RealView Emulation Baseboard User Guide for further information on baseboard signals.)

FPGA_nPROG

Configuration reload

The FPGA_nPROG signal forces all the FPGAs in the system to reconfigure.

GLOBAL_DONE

Configuration done

Open-collector signal that goes HIGH when all FPGAs have finished configuring. The system is held in reset until this signal goes HIGH.

nSYSPOR

Power-on resetThis is a post-configuration reset signal that is passed to all Logic Tiles in a stack. It is generated by the baseboard. It can be used to reset user logic if required. It remains active for between 1 and 10µS after GLOBAL_DONE goes HIGH.

D_nTRST

TAP controller reset

A system-wide, open collector signal that can be driven LOW by JTAG. This is the debug version of the nTRST signal.

It is connected to an FPGA input/output pin to provide a reset input to the virtual TAP controller. There are two possible sources of the D_nTRST signal:

  • JTAG connector

  • Trace (embedded trace macrocell) connector if supported.

D_nSRST

JTAG system reset

A system-wide, open collector signal that can be driven LOW by JTAG. This is the debug version of the nSRST signal.

C_nTRST

TAP controller reset

An open-collector signal that can be driven LOW by JTAG when using a Progcards utility to program the FPGA. (This signal is connected to FPGA_nPROG and forces the FPGA to reconfigure.) This is the config version of the nTRST signal.

C_nSRST

JTAG system reset

A system-wide, open-collector signal. This signal can be driven LOW by JTAG when using a Progcards utility to program the FPGA. (This signal is connected to the INIT pin of the FPGA.) This is the config version of the nSRST signal.

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