4.3. Configuring the FPGA from Flash

The Flash memory has space to store up to two configurations for Xilinx Virtex-4 FPGAs. The configuration image is selected when the Logic Tile is powered according to the setting of S2[2:1] and the FPGA_IMAGE signal from the motherboard:

Table 4.1 shows the FPGA image selection options.

Table 4.1. Image selection for XC4V FPGAs

S2[1]

S2[2]

FPGA_IMAGE signal

Flash image used

Image LED

Image base address

OFF

OFF

x

0

Unlit

0x000000

OFF

ON

x

1

Lit

0x800000

ON

x

00Unlit

0x000000

ON

x

11Lit

0x800000

Note

The positions of the switches have no effect on the Flash programming operation, only image selection on power-up.

See Application Note AN128 and Application Note AN170 on the Versatile CD for a description of the example lower and upper FPGA images respectively that are stored in Flash when the LT-XC4VLX100+ is shipped.

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