3.1. FPGA

The Logic Tile is fitted with a Xilinx Virtex-4 FPGA. The assignment of the input/output banks and JTAG implementation are described in the following sections:

For information about how the FPGA data is loaded, see Chapter 4 Configuring the FPGA and PLD.

At power-up the PLD loads configuration data for the FPGA from the on-board Flash memory. Parallel data from the Flash is streamed by the PLD into the configuration port (CFG_D[7:0]) of the FPGA, see PLD. It is also possible to load an image directly into the FPGA through the JTAG connector, but the image is lost when power is turned off.

Figure 3.1 is a simplified view of the tile and illustrates the function of the FPGA and shows how it connects to the other devices in the Logic Tile.

Figure 3.1. LT-XC4VLX100+ block diagram

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