3.1.1. FPGA I/O arrangement

The FPGA input/output pins are organized into 17 banks. Bank 0 is used for JTAG, configuration and miscellaneous functions and Banks 1 to 16 are routed to headers HDRX, HDRY, and HDRZ to support tile interconnection, The upper and lower HDRX, HDRY, and HDRZ header routing is shown in Figure 3.2 and Table 3.6 lists the bank I/O signal levels. See also Header signals for more details on I/O pins and header connections.

Figure 3.2. LT-XC4VLX100+ top and bottom header connections

Copyright © 2006-2008 ARM Limited. All rights reserved.ARM DUI 0345D
Non-Confidential