3.7. JTAG support

The Logic Tile does not have a JTAG connector. Use the connector on the baseboard or Interface Module:

There are two separate JTAG paths through the Logic Tile:

The JTAG path chosen depends on whether the system is in Configuration mode or Debug mode. The CONFIG link on the Interface Module or the CONFIG switch on the EB controls the nCFGEN signal that is routed through the Logic Tile connectors.

The nCFGEN signal selects between the following modes:

Figure 3.24 shows the JTAG data signal routing for an Integrator system. (The CONFIG link is closed, so the figure shows a system in Configuration mode.) Figure 3.25 shows the JTAG clock routing, and Figure 3.26 shows the JTAG TMS routing. Pull-up resistors are not shown on the drawings.

In Debug mode, the JTAG signals from the Interface Module are connected to FPGA input/output pins and enable you to implement a TAP controller in the FPGA design.

Note

If your design (or any other tile in the same stack) does not implement a TAP controller, then you must route TDI to TDO and TCK to RTCK in that design.

Figure 3.24. JTAG data paths

Figure 3.25. JTAG clock paths

Figure 3.26. JTAG TMS paths

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