4.1. Configuration system architecture

Configuration of the FPGA depends on the setting of the baseboard CONFIG switch at power on:


The FPGA is configured from the LT Flash memory under control of the configuration PLD.


If the baseboard CONFIG switch is ON, or the CONFIG link is fitted, the nCFGEN signal is active and you can use RealView ICE to download a configuration directly from the JTAG connector to the FPGA. This mechanism is also used by the Progcards utility to program a new FPGA configuration into the LT flash. It first loads a Flash programmer design into the FPGA and that writes the user bit file to the Flash memory.

Figure 4.1 shows the architecture of the FPGA configuration system and Figure 4.2 shows the reload timing sequence.


The FPGA_IMAGE signal is controlled by the baseboard. The baseboard image supplied by ARM selects the higher image in the Logic Tile Flash for the Logic Tile. To use the lower image in the Logic Tile Flash, set the image selection switches on the Logic Tile. See Configuring the FPGA from Flash for details.

Figure 4.1. Configuration system architecture

Figure 4.2. Reconfigure sequence


VBATT is the backup voltage to the FPGA encryption key circuitry within the FPGA. Removing the battery, entering a new encryption key, or shorting across the pads marked R2 erases the encryption key.

If the tile has been supplied with a preloaded encrypted image, the encryption key is required. If the key is erased, you must return the tile to ARM to have the key reloaded.

The battery is expected to last for approximately 10 years from manufacture of the tile. If you replace the battery, ensure that the positive terminal is facing upwards in the holder.

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