3.2. Header signals

This section gives an overview of the signals present on the header connectors. See About the LT-XC4VLX100+ Logic Tile for details of the board layout.

There are three headers on the top and bottom of the tile. The HDRX and HDRY headers are 180-way and the HDRZ connectors are 300-way. Signals that connect only to an upper header are identified by a U (for example, YU143), while signals that connect only to a lower header are identified by an L (for example XL179). Signals that go through both headers are not identified by a U or L (for example Z130). Figure 3.3 shows a simplified view of the header signal routing (clock, control, and JTAG signals on HDRZ are not shown).

Note

There is no correspondence between the header pin numbers and the generic signal numbers. For example, HDRY has generic signal YU113 on pin 48 of the upper connector.

The LT-XC4VLX100+ is fitted with either a Virtex-4 XC4VLX160-10 or XC4VLX200-10 device in a FFG1513 package. Both devices provide a maximum of 960 I/O pins. 918 of the pins are uncommitted and are connected directly to the Logic Tile headers for use in the user design. Table 3.1 lists the distribution of the 918 available I/O pins.

Table 3.1. I/O pin distribution

HeaderUpperLower
HDRX144144
HDRY144144
HDRZ107107
HDRZ through128128

For the signals on the upper and lower pins:

The header locations and pin numbering are shown in Header connectors.

Caution

The FPGA can be damaged if pins configured as outputs (on connected Logic Tiles or baseboards) are connected and output different logic levels.

Also, the signal input and output levels for many of the FPGA signals can be determined by an attached tile (see Variable I/O levels).

A further 30 of the remaining 42 FPGA I/O pins are generic to the ARM Logic Tile and Core Tile infrastructure. Table 3.2 lists the pins against signal type.

Table 3.2. Standard signals on HDRZ

SignalPins
External clocks21
JTAG7
Resets2

Table 3.3 lists the Virtex-4 FPGA external clocks I/O pins. See Clock architecture for further details on clocks.

Table 3.3. Virtex-4 FPGA External clocks

Pin name
CLK_POS_DN_OUT
CLK_NEG_DN_OUT
CLK_POS_UP_IN
CLK_NEG_UP_IN
CLK_IN_MINUS2
CLK_IN_MINUS1
CLK_GLOBAL_IN
CLK_GLOBAL_OUT
CLK_POS_DN_IN
CLK_NEG_DN_IN
CLK_POS_UP_OUT
CLK_NEG_UP_OUT
CLK_IN_PLUS2
CLK_IN_PLUS1
CLK_EXTERN
CLK_OUT_TO_BUF
CLK_BUF_LOOP
CLK_LOOP1_OUT
CLK_LOOP0_OUT
CLK_LOOP1_IN
CLK_LOOP0_IN

Table 3.4 lists the Virtex-4 JTAG I/O pins. See JTAG support for further details on JTAG.

Table 3.4. Virtex-4 FPGA JTAG

Pin name
D_nSRST
D_nTRST
FPGA_D_TDO
D_TDO_IN
FPGA_D_TCK
FPGA_D_TMS
FPGA_D_RTCK

Table 3.5 lists the Virtex-4 Resets I/O pins. See Reset control for further details on resets.

Table 3.5. Virtex-4 Resets

Pin name
nSYSPOR
nSYSRST

The remaining 12 I/O pins are used for:

Note

The configuration pins are re-used when the Logic Tile is in Debug mode to provide additional interconnect between the FPGA and the PLD. This is used for LEDs, switches, clocks and control, and a serial interface to the PLD.

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